Progress and trends of low-jitter fractional-N PLL
Authors: Jun Yin, Haoran Li, Xiaoqi Lin, Rui P. Martins, Pui-In Mak
Fractional-N phase-locked loops (PLLs) are widely deployed in high-speed communication systems to generate local oscillator (LO) or clock signals with precise frequency. To support sophisticated modulations for increasing the data rate, the PLL needs to generate low-jitter output. Since the output frequency of the fractional-N PLL is not an integer multiple of the reference clock frequency, the phase error seen by the phase detector (PD) contains not only a random part induced by the oscillator and loop noise, but also a deterministic part due to the fractional operation, which is referred to as the quantization error (Q-error). The Q-error has two side effects on the output jitter. Firstly, the Q-error will induce quantization noise in the PLL output. Although the energy of quantization noise can be shaped to high offset frequencies and suppressed by the low-pass characteristics of the loop with the aid of a delta-sigma modulator (DSM), it could still contribute a substantial portion of the output jitter if a moderate or large loop bandwidth is required to suppress the oscillator's phase noise (PN). Secondly, when the Q-error passes through a nonlinear PD, fractional spurs will be generated, and quantization noise at high offset frequencies will be folded into in-band, which also degrades the output jitter. These side effects could limit the jitter performance in fractional-N PLLs. In the following sections, recent techniques to minimize the side effects of Q-error that enable low-jitter fractional-N PLL with high power efficiency will be reviewed.
