• Fractional-N PLLs suffer from quantization error (Q-error) that induces quantization noise and fractional spurs, degrading output jitter.
• Techniques such as offset PFD-CP and enhanced DSM (ENOP) can suppress fractional spurs and noise folding, achieving low jitter.
• Small loop bandwidth and large CP current are required to filter quantization noise and lower in-band phase noise, but they demand large capacitors and low-PN VCOs.
• Advanced CMOS technologies with reduced supply voltage pose challenges for implementing low-jitter fractional-N PLLs with high power efficiency.