Key Takeaways & Executive Findings
- •• Vertical power delivery (VPD) with multi-chip multi-phase DC−DC converters enables core rail currents exceeding 2 kA and reduces PDN losses, saving >100 W per processor. • A two-stage 48 V to sub-1 V conversion architecture, combining an LLC DCX and an ultra-thin multiphase buck, achieves high power density and fast transient response. • The choice of interconnection topology (ring, chain, or net) and control scheme (independent or master-slave) significantly impacts scalability, fault tolerance, and current sharing in multi-chip converters. • Advanced packaging and 48 V architectures are key to meeting AI power demands while reducing carbon footprint in large-scale datacenters.
Abstract
As artificial intelligence (AI) workloads escalate exponentially, ultra-thin, high-efficiency voltage regulator modules (VRMs) with exceptional power density become essential for backside-mounted configurations. High-density multiphase DC−DC converters are pivotal for implementing vertical power delivery (VPD) architectures in XPU platforms. Strategically positioning these converters beneath processors and maximizing spatial utilization enables core rail currents exceeding 2 kA while significantly reducing power distribution network (PDN) losses compared to conventional solutions. The VPD configuration elevates system-level energy efficiency with >100 W power saving per processor, yielding megawatt-scale savings in a datacenter that uses ~100 000 processors. The synergy of 48 V power conversion architectures and advanced packaging techniques enables the industry’s commitment to balancing computational demands with CO2 emission reduction and environmental sustainability. This paper discusses system architecture, layout geometry, and control strategies for multi-chip multi-phase DC−DC converters, comparing ring, chain, and net topologies, as well as independent and master-slave control schemes.
1. Introduction
As artificial intelligence (AI) workloads escalate exponentially, ultra-thin, high-efficiency voltage regulator modules (VRMs) with exceptional power density become essential for backside-mounted configurations. High-density multiphase DC−DC converters are pivotal for implementing vertical power delivery (VPD) architectures in XPU platforms. Strategically positioning these converters beneath processors and maximizing spatial utilization enables core rail currents exceeding 2 kA while significantly reducing the power distribution network (PDN) losses compared to conventional solutions.
The VPD configuration elevates system-level energy efficiency with >100 W power saving per processor, yielding megawatt-scale savings in a datacenter that uses ~100 000 processors. The synergy of 48 V power conversion architectures and advanced packaging techniques enables the industry’s commitment to balancing computational demands with CO2 emission reduction and environmental sustainability.
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Yan Lu, Zhiguo Tong, Jiacheng Yang, Zhewen Yu, Mo Huang, Xiangyu Mao (2025). Multi-chip multi-phase DC−DC converters for AI power: a ring, a chain, or a net, independent or master-slave?. SinoTechIntel Verified Research. https://doi.org/10.1088/1674-4926/25040033
Research & Educational Purpose Only:The translations, structured abstracts, analytical annotations, and data reports provided by SinoTechIntel are intended exclusively for academic research, internal corporate R&D, and educational benchmarking. They do not constitute formal engineering, chemical safety, legal, or professional advice.
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Frequently Asked Questions
What is vertical power delivery (VPD) and how does it benefit AI processors?
Vertical power delivery (VPD) places DC-DC converters directly beneath the processor, reducing power distribution network (PDN) losses and enabling core rail currents exceeding 2 kA. This configuration saves over 100 W per processor, leading to megawatt-scale savings in large datacenters.
What are the common topologies for multi-chip multi-phase DC-DC converters?
The paper discusses ring, chain, and net topologies for interconnecting multiple converter chips. Each topology offers different trade-offs in terms of current sharing, fault tolerance, and scalability.
What is the difference between independent and master-slave control in multi-chip converters?
Independent control allows each chip to operate autonomously, while master-slave control designates one chip as the master to synchronize and coordinate the others. The choice affects system complexity, reliability, and performance.
Why is a two-stage 48 V to sub-1 V conversion architecture recommended?
A two-stage architecture, using an LLC resonant converter as an unregulated DC transformer (DCX) followed by an ultra-thin multiphase buck, achieves high power density, high efficiency, and fast transient response, which are critical for AI power delivery.
How does advanced packaging contribute to AI power efficiency?
Advanced packaging techniques, such as 3D integration and backside mounting, reduce parasitic losses and improve thermal management, enabling higher power density and efficiency in DC-DC converters for AI applications.
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