Key Takeaways & Executive Findings
- •• Fractional-N PLLs suffer from quantization error (Q-error) that induces quantization noise and fractional spurs, degrading output jitter. • Techniques such as offset PFD-CP and enhanced DSM (ENOP) can suppress fractional spurs and noise folding, achieving low jitter. • Small loop bandwidth and large CP current are required to filter quantization noise and lower in-band phase noise, but they demand large capacitors and low-PN VCOs. • Advanced CMOS technologies with reduced supply voltage pose challenges for implementing low-jitter fractional-N PLLs with high power efficiency.
Abstract
Fractional-N phase-locked loops (PLLs) are widely deployed in high-speed communication systems to generate local oscillator (LO) or clock signals with precise frequency. To support sophisticated modulations for increasing the data rate, the PLL needs to generate low-jitter output. Since the output frequency of the fractional-N PLL is not an integer multiple of the reference clock frequency, the phase error seen by the phase detector (PD) contains not only a random part induced by the oscillator and loop noise, but also a deterministic part due to the fractional operation, which is referred to as the quantization error (Q-error). The Q-error has two side effects on the output jitter. Firstly, the Q-error will induce quantization noise in the PLL output. Although the energy of quantization noise can be shaped to high offset frequencies and suppressed by the low-pass characteristics of the loop with the aid of a delta-sigma modulator (DSM), it could still contribute a substantial portion of the output jitter if a moderate or large loop bandwidth is required to suppress the oscillator's phase noise (PN). Secondly, when the Q-error passes through a nonlinear PD, fractional spurs will be generated, and quantization noise at high offset frequencies will be folded into in-band, which also degrades the output jitter. These side effects could limit the jitter performance in fractional-N PLLs. In the following sections, recent techniques to minimize the side effects of Q-error that enable low-jitter fractional-N PLL with high power efficiency will be reviewed.
1. Introduction
Fractional-N phase-locked loops (PLLs) are widely deployed in high-speed communication systems to generate local oscillator (LO) or clock signals with precise frequency. To support sophisticated modulations for increasing the data rate, the PLL needs to generate low-jitter output. Since the output frequency of the fractional-N PLL is not an integer multiple of the reference clock frequency, the phase error seen by the phase detector (PD) contains not only a random part induced by the oscillator and loop noise, but also a deterministic part due to the fractional operation, which is referred to as the quantization error (Q-error).
The Q-error has two side effects on the output jitter. Firstly, the Q-error will induce quantization noise in the PLL output. Although the energy of quantization noise can be shaped to high offset frequencies and suppressed by the low-pass characteristics of the loop with the aid of a delta-sigma modulator (DSM), it could still contribute a substantial portion of the output jitter if a moderate or large loop bandwidth is required to suppress the oscillator's phase noise (PN). Secondly, when the Q-error passes through a nonlinear PD, fractional spurs will be generated, and quantization noise at high offset frequencies will be folded into in-band, which also degrades the output jitter. These side effects could limit the jitter performance in fractional-N PLLs. In the following sections, recent techniques to minimize the side effects of Q-error that enable low-jitter fractional-N PLL with high power efficiency will be reviewed.
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Jun Yin, Haoran Li, Xiaoqi Lin, Rui P. Martins, Pui-In Mak (2025). Progress and trends of low-jitter fractional-N PLL. SinoTechIntel Verified Research. https://doi.org/10.1088/1674-4926/25040035
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Frequently Asked Questions
What is the main challenge in fractional-N PLLs?
The main challenge is the quantization error (Q-error) caused by the fractional operation, which induces quantization noise and fractional spurs, degrading output jitter.
How does the Q-error affect output jitter?
The Q-error induces quantization noise that can contribute to output jitter, and when passing through a nonlinear phase detector, it generates fractional spurs and folds high-frequency noise into the in-band, further degrading jitter.
What techniques are used to reduce Q-error effects?
Techniques include using an offset PFD-CP to avoid crossover nonlinearity, employing enhanced delta-sigma modulators (ENOP) to reduce fractional spurs, and optimizing loop bandwidth and charge pump current to filter quantization noise.
Why is a small loop bandwidth required in some designs?
A small loop bandwidth is required to filter the quantization noise from the delta-sigma modulator, but it demands a very low phase noise VCO to avoid dominating jitter, often leading to large power consumption.
What are the trade-offs in low-jitter fractional-N PLL design?
Trade-offs include between loop bandwidth and quantization noise filtering, between charge pump current and in-band phase noise, and between VCO phase noise and power consumption, especially in advanced CMOS with reduced supply voltage.
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