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🏛️ Indexed Academic JournalImpact Factor: 2.7 (Q2 - Springer)

ENGINEERING Information Technology & Electronic Engineering

2.7 (Q2 - Springer)

Total Research Papers: 153
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Published Research PapersFiltered: Year 2025 • Vol. 32 • Issue 5

Showing 13 of 153 peer-reviewed papers with full Graphical Abstracts.

Original ResearchVol. 32, Issue 5 • pp. 372-384DOI: 10.1631/ENG_ITEE_2025_0081• May 24, 2025

TP-ViT: truncated uniform-log2 quantizer and progressive bit-decline reconstruction for vision Transformer quantization

Authors: Xichuan ZHOU, Sihuan ZHAO, Rui DING, Jiayu SHI, Jing NIE, Lihui CHEN, Haijun LIU

Vision Transformers (ViTs) have achieved remarkable success across various artificial intelligence-based computer vision applications. However, their demanding computational and memory requirements pose significant challenges for deployment on resource-constrained edge devices. Although post-training quantization (PTQ) provides a promising solution by reducing model precision with minimal calibration data, aggressive low-bit quantization typically leads to substantial performance degradation. To

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TP-ViT: truncated uniform-log2 quantizer and progressive bit-decline reconstruction for vision Transformer quantization
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Original ResearchVol. 32, Issue 5 • pp. 608-620DOI: 10.1631/FITEE_2401012• May 23, 2025

Full-defense framework: multi-level deepfake detection and source tracing

Authors: Hui SHI, Guibin WANG, Yanni LI, Rujia QI

Deepfake poses significant threats to various fields, including politics, journalism, and entertainment. Although many defense methods against deepfake have been proposed based on either passive detection or proactive defense, few have achieved both passive detection and proactive defense. To address this issue, we propose a full-defense framework (FDF) based on cross-domain feature fusion and separable watermarks (SepMark) to achieve copyright protection and deepfake detection, combining the id

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Full-defense framework: multi-level deepfake detection and source tracing
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Original ResearchVol. 32, Issue 5 • pp. 780-792DOI: 10.1631/ENG_ITEE_2025_0156• May 21, 2025

HyRAS: a hybrid redundancy- and serialization-based fault-tolerant architecture for through-silicon vias

Authors: Chenglong SUN, Yanqing ZHOU, Qi WANG, Yan ZHANG

Three-dimensional network-on-chips (3D NoCs) are increasingly used to improve scalability in multicore systems. Through-silicon via (TSV) is a critical technology for enabling vertical interconnects between NoC layers. However, TSV-based interlayer connections are highly prone to faults resulting from manufacturing defects, aging, or other sources, which compromise system reliability. To address these challenges, particularly in chiplet-based 3D NoCs, robust fault-tolerant mechanisms are crucial

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HyRAS: a hybrid redundancy- and serialization-based fault-tolerant architecture for through-silicon vias
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Original ResearchVol. 32, Issue 5 • pp. 216-228DOI: 10.1631/FITEE_2530000• May 20, 2025

Engineering and technology for low-altitude economy infrastructure

Authors: Zhijie Chen, Heung-Yeung Shum, Xianbin Cao, Mark Hansen

The market of low-altitude economy has the potential to reach trillion dollars in 10 years globally. In China, it serves as a hallmark of national strategic emerging industries, and represents new quality productive forces. Exploring innovative engineering and technologies for low-altitude economy infrastructure is expected to promote sustainable growth in this sector. The scope of the low-altitude economy spans from the ground to the air, with its infrastructure encompassing various aspects suc

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Engineering and technology for low-altitude economy infrastructure
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Original ResearchVol. 32, Issue 5 • pp. 388-400DOI: 10.1631/FITEE_2400102• May 18, 2025

XIRAC: an optimized product-oriented near-real-time operating system with unlimited tasks and an innovative programming paradigm based on the maximum entropy method

Authors: Alireza ZIRAK

In the fiercely competitive landscape of product-oriented operating systems, including the Internet of Things (IoT), efficiently managing a substantial stream of real-time tasks coexisting with resource-intensive user applications embedded in constrained hardware presents a significant challenge. Bridging the gap between embedded and general-purpose operating systems, we introduce XIRAC, an optimized operating system shaped by information-theory principles. XIRAC leverages Shannon’s information

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XIRAC: an optimized product-oriented near-real-time operating system with unlimited tasks and an innovative programming paradigm based on the maximum entropy method
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Original ResearchVol. 32, Issue 5 • pp. 796-808DOI: 10.1631/FITEE_2400547• May 15, 2025

An end-to-end automatic methodology to accelerate the accuracy evaluation of deep neural networks under hardware transient faults

Authors: Jiajia JIAO, Ran WEN, Hong YANG

Hardware transient faults are proven to have a significant impact on deep neural networks (DNNs), whose safety-critical misclassification (SCM) in autonomous vehicles, healthcare, and space applications is increased up to four times. However, the inaccuracy evaluation using accurate fault injection is time-consuming and requires several hours and even a couple of days on a complete simulation platform. To accelerate the evaluation of hardware transient faults on DNNs, we design a unified and end

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An end-to-end automatic methodology to accelerate the accuracy evaluation of deep neural networks under hardware transient faults
Graphical Abstract
Original ResearchVol. 32, Issue 5 • pp. 404-416DOI: 10.1631/FITEE_2400677• May 12, 2025

Algorithm and evaluation of generating pseudo-datasets for integrated circuit power analysis

Authors: Zejia Lyu, Jizhong Shen, Xi Chen

Average power analysis plays a crucial role in the design of large-scale digital integrated circuits (ICs). The integration of data-driven machine learning (ML) methods into the electronic design automation (EDA) fields has increased the demand for extensive datasets. To address this need, we propose a novel pseudo-circuit generation algorithm rooted in graph topology. This algorithm efficiently produces a multitude of power analysis examples by converting randomly generated directed acyclic gra

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Algorithm and evaluation of generating pseudo-datasets for integrated circuit power analysis
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Original ResearchVol. 32, Issue 5 • pp. 576-588DOI: 10.1631/ENG_ITEE_2025_0047• May 10, 2025

DDiNER: domain dictionary-guided Chinese named entity recognition for complex industrial contexts

Authors: Ronghui LIU, Wei CUI, Xiaojun LIANG, Weihua GUI

Accurate Chinese named entity recognition (NER) in the process industry is crucial for applications such as information extraction, knowledge graph construction, and intelligent decision-making. However, challenges, including ambiguous entity boundaries, semantic overlaps, and limited annotated data, significantly hinder performance. To address these issues, this study proposes DDiNER, a domain dictionary-guided Chinese NER framework that integrates a hierarchical industrial domain dictionary wi

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DDiNER: domain dictionary-guided Chinese named entity recognition for complex industrial contexts
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Original ResearchVol. 32, Issue 5 • pp. 812-824DOI: 10.1631/FITEE_2500582• May 9, 2025

AI-agent communication network for 6G: vision, architecture, and key technologies

Authors: Xiaodong Duan, Zhenglei Huang, Shiyu Liang, Shaowen Zheng, Lu Lu, Tao Sun

The booming of artificial intelligence (AI) agents has brought about promising business scenarios for sixth-generation (6G) mobile networks, while simultaneously posing significant challenges to network functionalities and infrastructure. These AI agents can be deployed on end devices (e.g., intelligent robots and intelligent cars) or as digital entities (e.g., personal AI assistants). As novel service entities with autonomous decision-making and task execution capabilities, AI agents introduce

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AI-agent communication network for 6G: vision, architecture, and key technologies
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Original ResearchVol. 32, Issue 5 • pp. 184-196DOI: 10.1631/FITEE_2300795• May 7, 2025

A review of flexible job shop scheduling problems considering transportation vehicles

Authors: Bin Xin, Sai Lu, Qing Wang, Fang Deng

The flexible job shop scheduling problem for processing machines and transportation vehicles (FJSP_PT) has garnered significant attention from academia and industry. Due to the inclusion of transportation vehicle scheduling in the scheduling problem of flexible manufacturing systems, solving FJSP_PT becomes more challenging and significantly more practically relevant compared to the flexible job shop scheduling problem. We summarize the assumptions, constraints, objective functions, and benchmar

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A review of flexible job shop scheduling problems considering transportation vehicles
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Original ResearchVol. 32, Issue 5 • pp. 420-432DOI: 10.1631/FITEE_2500353• May 6, 2025

Robust design for IRS-assisted multiuser systems under practical imperfections: a rate-splitting approach

Authors: Xingyu Peng, Qin Tao, Xiaoming Chen

In practical intelligent reflecting surface (IRS)-assisted multiuser communication systems, inevitable imperfections such as hardware impairments, imperfect channel state information (CSI), and the limited resolution of the IRS phase shifts would introduce interference and thus cause significant performance degradation. As an interference management strategy, rate-splitting multiple access (RSMA) employs the rate-splitting (RS) principle to partition user information into common and private part

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Robust design for IRS-assisted multiuser systems under practical imperfections: a rate-splitting approach
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Original ResearchVol. 32, Issue 5 • pp. 592-604DOI: 10.1631/FITEE_2400602• May 4, 2025

Memory-efficient tensor parallelism for long-sequence Transformer training

Authors: Peng LIANG, Linbo QIAO, Yanqi SHI, Hao ZHENG, Yu TANG, Dongsheng LI

Transformer-based models like large language models (LLMs) have attracted significant attention in recent years due to their superior performance. A long sequence of input tokens is essential for industrial LLMs to provide better user services. However, memory consumption increases quadratically with the increase of sequence length, posing challenges for scaling up long-sequence training. Current parallelism methods produce duplicated tensors during execution, leaving space for improving memory

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Memory-efficient tensor parallelism for long-sequence Transformer training
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Original ResearchVol. 32, Issue 5 • pp. 200-212DOI: 10.1631/FITEE_2400613• May 1, 2025

An optimized formula for the two-point resistance of a cobweb resistance network and its potential application

Authors: Yu Guan, Xiaoyu Jiang, Yanpeng Zheng, Zhaolin Jiang

In recent years, the exploration and application of resistance networks have expanded significantly, and solving the equivalent resistance between two points of a resistance network has been an important topic. In this paper, we focus on optimizing the formula for calculating the two-point resistance of an m × n cobweb resistance network with 2r boundary conditions. To improve the computational efficiency of the equivalent resistance between two points, the formula is optimized by using the opti

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An optimized formula for the two-point resistance of a cobweb resistance network and its potential application
Graphical Abstract