HyRAS: a hybrid redundancy- and serialization-based fault-tolerant architecture for through-silicon vias

Abstract

Three-dimensional network-on-chips (3D NoCs) are increasingly used to improve scalability in multicore systems. Through-silicon via (TSV) is a critical technology for enabling vertical interconnects between NoC layers. However, TSV-based interlayer connections are highly prone to faults resulting from manufacturing defects, aging, or other sources, which compromise system reliability. To address these challenges, particularly in chiplet-based 3D NoCs, robust fault-tolerant mechanisms are crucial for maintaining operational integrity in the presence of TSV faults. We introduce a novel fault-tolerant architecture designed to ensure persistent communication reliability despite permanent vertical link failures, named HyRAS, a hybrid redundancy- and serialization-based method. Our approach is built on two synergistic mechanisms. First, a lightweight spatial redundancy-based scheme leverages shared TSV resources to mitigate the impact of isolated faults. Second, for more severe fault scenarios, an adaptive serialization-based strategy is employed to maintain connectivity by efficiently using the remaining functional links. The architecture is rigorously evaluated through functional simulations using both synthetic traffic patterns and realistic application workloads. Compared to contemporary fault-tolerant methods, HyRAS achieves up to 28.2% higher throughput under realistic workloads with significant defect clusters. These gains are achieved with only modest overhead, incurring a 14.53% increase in area and 8.87% increase in power consumption relative to the standard redundancy-based router.

1. Introduction

The relentless drive for greater computational power has spurred an architectural shift from computation-centric designs to communication-centric paradigms. In this landscape, network-on-chips (NoCs) have become the de facto interconnect standard for modern multicore systems (Agarwal et al., 2025; Xiong et al., 2025). To push beyond the limits of two-dimensional (2D) circuits, three-dimensional (3D) integration has emerged, stacking multiple device layers and connecting them with high-speed vertical interconnects. The primary advantage of 3D NoCs is the substantial reduction in global interconnect length, which translates to higher performance and lower power dissipation (Bose and Ghosal, 2020; Fu et al., 2021; Taheri et al., 2023).

However, the development of 3D NoCs comes with many unavoidable challenges. The combination of shrinking process nodes, complex 3D packaging, and higher operating frequencies exacerbates error rates, thermal issues, and timing violations. Among the critical components of 3D integrated circuits (3D-ICs), through-silicon vias (TSVs) are favored for their high-speed and low-power vertical communication capabilities. However, as system complexity grows, so does the threat to reliability. The TSV manufacturing process is notoriously prone to defects, leading to permanent (or hard) faults that can arise during fabrication or from operational stresses such as time-dependent dielectric breakdown (TDDB), electromigration, and thermal cycling (Dang et al., 2020a; da Silva et al., 2025). To address these challenges, various studies have proposed dependable NoC architectures to guarantee strong system performance.

Among the vertical interconnection technologies enabling 3D-ICs, TSV has been widely adopted due to the capacity for high-speed and power-efficient communication between layers. As single-chip designs advance toward peta-scale computation performance, with exascale systems anticipated in the coming decade, system reliability has emerged as a critical challenge. The reliability of on-chip architectures is negatively impacted by increasing power consumption, process variability, and component density. For instance, rapid fluctuations in power consumption can induce on-chip voltage variations, leading to data transmission errors (Hou et al., 2024). Permanent faults, also known as hard faults, occur during manufacturing or operation and persistently disrupt circuit functionality from their moment of onset. The primary physical mechanisms contributing to these permanent faults include TDDB, negative bias temperature instability (NBTI), hot carrier injection (HCI), and electromigration, all of which are driven by mate