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Official PDF TranslationEngineering Information Technology & Electronic Engineering

HyRAS: a hybrid redundancy- and serialization-based fault-tolerant architecture for through-silicon vias

Authors: Chenglong SUN; Yanqing ZHOU; Qi WANG; Yan ZHANG

DOI: 10.1631/ENG_ITEE_2025_0156Status: Verified Translated Edition
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Key Findings in This Report

• HyRAS introduces a hybrid fault-tolerant architecture that combines lightweight spatial redundancy and adaptive serialization to maintain communication in chiplet-based 3D NoCs despite permanent TSV faults. • The spatial redundancy mechanism leverages shared TSV resources to handle isolated faults, while adaptive serialization ensures connectivity under severe fault scenarios. • Functional simulations under realistic workloads with significant defect clusters show up to 28.2% higher throughput compared to contemporary fault-tolerant methods. • The architecture incurs modest overheads: a 14.53% increase in area and an 8.87% increase in power relative to a standard redundancy-based router.