• Design of a novel graph-topology-based pseudo-circuit generation algorithm that produces diverse power analysis examples for ML-driven EDA.
• Efficient conversion of random directed acyclic graphs into gate-level Verilog pseudo-combinational and pseudo-sequential netlists with controllable hyperparameters.
• Validation via mainstream power analysis tools, benchmark comparison, topology complexity analysis, and static timing analysis.
• Demonstrates the dataset's effectiveness and algorithmic robustness, providing a scalable solution for data-hungry machine learning models in IC power estimation.