Algorithm and evaluation of generating pseudo-datasets for integrated circuit power analysis

Abstract

Average power analysis plays a crucial role in the design of large-scale digital integrated circuits (ICs). The integration of data-driven machine learning (ML) methods into the electronic design automation (EDA) fields has increased the demand for extensive datasets. To address this need, we propose a novel pseudo-circuit generation algorithm rooted in graph topology. This algorithm efficiently produces a multitude of power analysis examples by converting randomly generated directed acyclic graphs (DAGs) into gate-level Verilog pseudo-combinational circuit netlists. The subsequent introduction of register units transforms pseudo-combinational netlists into pseudo-sequential circuit netlists. Hyperparameters facilitate the control of circuit topology, while appropriate sequential constraints are applied during synthesis to yield a pseudo-circuit dataset. We evaluate our approach using the mainstream power analysis software, conducting pre-layout average power tests on the generated circuits, comparing their performance against benchmark datasets, and verifying the results through circuit topology complexity analysis and static timing analysis (STA). The results confirm the effectiveness of the dataset, and demonstrate the operational efficiency and robustness of the algorithm, underscoring its research value.

1. Introduction

Power analysis plays a pivotal role in the design of large-scale digital integrated circuits (ICs), where accurate and efficient power evaluation during the design phase can substantially improve chip performance. In the industry, power analysis typically refers to average power estimation facilitated by the electronic design automation (EDA) software. Notable examples of commercial software for this purpose include Synopsys PrimeTime PX (PTPX) and Cadence Voltus. Typically, average power analysis is performed at the gate level, where power is calculated based on circuit activity.

Circuit activity can be categorized into annotated and vectorless types. The annotated method uses simulators like Synopsys Verilog compiled simulator (VCS) with predefined test vectors to monitor activity at each circuit node, typically recorded in switching activity interchange format (SAIF) files. Although the simulation-based annotated method offers high accuracy, it is time-consuming and demands significant storage space. Consequently, the industry often employs a vectorless method in the pre-simulation phase, which uses a mathematical model to estimate the activity probability at each node and then computes power consumption.

The concept of probability-based power estimation was first introduced by Najm (1993), and has since spurred extensive research within the academic community on such theoretical models (Burch et al., 1992; Xie, 2023). These models are used solely for algorithm validation, and do not require large case sizes. However, as circuit complexity escalates, traditional algorithms struggle with efficiency and accuracy, particularly in large-scale combinational and sequential circuits. This challenge has led to a growing interest in data-driven machine learning (ML) approaches. Several researchers have explored innovative methods; for instance, Zhou Y et al. (2019) introduced power inference using machine learning (PRIMAL), using convolutional networks for power estimation, while Kumar and Gerstlauer (2019) adopted a decision tree approach. Others like Zhang et al. (2020), Rakesh et al. (2023), and Khan et al. (2024) employed graph neural networks to represent circuit topology for power prediction, while Li et al. (2022), Fang et al. (2023), and Kumar et al. (2023) used traditional neural networks. In addition to the mentioned power prediction, there are circuit power optimization methods, such as the ML-based circuit power optimization proposed by Zou et al. (2024).