Key Takeaways & Executive Findings
- •• Chinese 8-inch 4H-SiC substrate yields average 35-45% usable area due to micropipe densities of 0.3-0.5 cm^-2, versus 60% for Wolfspeed's 6-inch, delaying cost parity. • Domestic epitaxy (Naura, CETC) achieves 85-90% BPD-to-TED conversion, below the >95% threshold needed to prevent bipolar degradation in 1,200V+ MOSFETs. • Beta-Ga2O3's Baliga figure of merit is 3x SiC, but its thermal conductivity (0.23 W/m·K) forces 3x die area for 10kV switches, negating cost advantages. • An 8-inch SiC fab requires $800M+ CAPEX for 100k wafers/year; Ga2O3 could cut substrate cost by 80%, but no commercial 4-inch substrates exist yet. • China's equipment push (Naura, CETC) is closing the gap in epitaxy and ion implantation, but crystal growth remains the bottleneck, with 6-inch SiC still dominant.
Introduction: The 8-Inch SiC and Ga2O3 Race
China's power semiconductor industry is at a crossroads. The global shift to electric vehicles and renewable energy demands high-efficiency power switches rated at 1,200V to 3,300V. Silicon carbide (SiC) is the incumbent, but its high cost and substrate defects limit adoption. Meanwhile, beta-gallium oxide (β-Ga2O3) promises higher performance at lower cost, yet its thermal limitations remain unsolved. This report examines the empirical state of 8-inch 4H-SiC substrate manufacturing in China and the emerging β-Ga2O3 alternative, focusing on yield optimization and equipment readiness.
8-Inch 4H-SiC Substrate Growth: The Yield Bottleneck
Physical Vapor Transport (PVT) remains the dominant method for growing 4H-SiC boules. At temperatures exceeding 2,400°C, a seed crystal is exposed to a silicon-carbon vapor, growing at rates of 0.3-0.5 mm/hour. The critical challenge is maintaining a uniform axial thermal gradient—ideally below 5°C/cm—to prevent micropipe formation. Micropipes are hollow core dislocations that act as leakage paths in devices; for automotive-grade substrates, the density must be below 0.1 cm^-2.
Chinese manufacturers (SICC, TankeBlue, and others) have scaled to 8-inch, but the data is sobering. Typical micropipe densities range from 0.3 to 0.5 cm^-2, resulting in usable areas of only 35-45% per wafer. In contrast, Wolfspeed's 6-inch lines achieve >60% usable area with micropipe densities <0.05 cm^-2. The yield loss is not just from micropipes—basal plane dislocations (BPDs) also propagate, and their density must be controlled during epitaxy.
The arithmetic does not work for Western refiners. An 8-inch SiC wafer costs $2,500 to produce, but with 40% yield, the effective cost per good die is 2.5x higher than a 6-inch wafer with 60% yield. China's cost advantage in labor and electricity is offset by this yield gap.
To improve yields, Chinese researchers are experimenting with seed crystal quality, crucible design, and post-growth annealing. For instance, SICC reported a 15% yield improvement by using a dual-seed technique and optimizing the thermal field with numerical simulations. However, the industry standard for 8-inch is still evolving, and no Chinese manufacturer has yet achieved volume production with yields above 50%.
Epitaxial Layer Deposition: BPD-to-TED Conversion
Once the substrate is sliced, an epitaxial layer is grown via chemical vapor deposition (CVD). This step is crucial for device performance. During epitaxy, BPDs from the substrate can either propagate into the epilayer or convert to threading edge dislocations (TEDs). TEDs are benign, but BPDs cause stacking faults under forward bias, leading to bipolar degradation—a gradual increase in on-resistance that can reach 15% after 1,000 hours of operation in 1,200V MOSFETs.
The conversion rate depends on the growth conditions: temperature (1,600-1,700°C), pressure (50-100 mbar), and the C/Si ratio. High-quality epi-reactors from Aixtron (G5 WW C2) and Veeco achieve >95% conversion by using a deliberate buffer layer and optimized in-situ etching. Chinese equipment from Naura and CETC has improved, but their reactors still lag: conversion rates of 85-90% are typical. This 5-10% difference translates to a higher failure rate in automotive applications, where long-term reliability is non-negotiable.
Sanan Optoelectronics, a leading Chinese foundry, has installed both domestic and imported reactors. In a recent audit, their domestic reactors produced epiwafers with a BPD density of 0.5 cm^-2, versus 0.1 cm^-2 for Aixtron systems. The gap is narrowing, but it underscores the need for process optimization.
Beta-Ga2O3: The Ultra-Wide Bandgap Contender
β-Ga2O3 has emerged as a promising material for ultra-high-voltage applications (>10kV) due to its bandgap of 4.8 eV and breakdown field of 8 MV/cm. Its Baliga figure of merit (BFOM) is 3x that of 4H-SiC, meaning lower conduction losses for the same voltage rating. Moreover, β-Ga2O3 can be grown from melt using Edge-defined Film-fed Growth (EFG), which is faster and cheaper than PVT. Substrate costs are estimated at 1/5th of SiC, a significant advantage.
However, the material has a critical flaw: thermal conductivity of only 0.23 W/m·K, compared to 490 W/m·K for SiC. This means heat generated in the device cannot dissipate effectively, leading to thermal runaway unless the die is oversized or advanced cooling is used. For a 10kV switch, simulations show that a β-Ga2O3 die would need to be 3x larger than a SiC die to maintain junction temperatures below 150°C, negating the cost advantage.
Chinese research institutions, including CETC and several universities, have grown 2-inch β-Ga2O3 crystals with 5N purity using EFG. Pilot lines at Sanan and CETC are producing test devices, but 4-inch substrates remain elusive. The growth process is plagued by cracking due to thermal stress, and the crystal's cleavage planes make wafer handling difficult. Furthermore, no commercial epitaxy equipment exists for β-Ga2O3; researchers use modified MOCVD or mist-CVD systems.
Equipment Ecosystem: Domestic vs. Imported
China's push for self-sufficiency in semiconductor equipment has yielded progress in SiC epitaxy. Naura's epi-reactors are now installed in several fabs, and CETC has developed high-energy ion implanters for SiC. However, for crystal growth, the dominant equipment is still imported from companies like LPE (Italy) and Aymont (now part of SKC). Domestic PVT furnaces exist but lack the thermal uniformity needed for 8-inch boules.
In contrast, for β-Ga2O3, the equipment is largely homegrown because no commercial market exists yet. CETC has built custom EFG furnaces, and Sanan has developed its own MOCVD processes. This gives China a potential first-mover advantage in β-Ga2O3, but the material's thermal issues remain a barrier.
Engineering Comparison: 4H-SiC vs. GaN vs. β-Ga2O3 vs. Diamond
| Material | Bandgap (eV) | Breakdown Field (MV/cm) | Thermal Conductivity (W/m·K) | Commercial Wafer Size |
|---|---|---|---|---|
| 4H-SiC | 3.26 | 3.0 | 490 | 6-inch (150mm), 8-inch emerging |
| GaN | 3.4 | 3.3 | 130 (bulk) | 2-inch (native), 6-inch on Si |
| β-Ga2O3 | 4.8 | 8.0 | 0.23 | 2-inch (research), 4-inch in development |
| Diamond | 5.5 | 10.0 | 2000 | None (research only) |
The table illustrates the trade-offs. SiC offers a balanced profile, which is why it dominates. GaN excels in high-frequency applications but lacks vertical devices for high voltage. β-Ga2O3 has superior electrical properties but terrible thermal performance. Diamond is ideal but impossible to grow economically.
Economic Analysis: CAPEX and Cost per Wafer
Building an 8-inch SiC fab with a capacity of 100,000 wafers per year requires an estimated CAPEX of $800 million, including crystal growth, epitaxy, and device fabrication. In contrast, a β-Ga2O3 fab could be built for $400 million due to lower substrate costs and simpler growth equipment. However, the lack of mature process technology and the need for die oversizing to manage heat could erode these savings.
For SiC, the cost per wafer is dominated by substrate growth. A 6-inch wafer costs around $1,000, while an 8-inch wafer costs $2,500. With yields of 60% for 6-inch and 40% for 8-inch, the cost per good die is $1,667 vs. $6,250—a 3.75x difference. This explains why many Chinese fabs are sticking with 6-inch for now.
Conclusion: The Path Forward
China's wide-bandgap strategy is twofold: improve 8-inch SiC yields to compete on cost, and develop β-Ga2O3 to leapfrog in ultra-high-voltage applications. The former requires mastering crystal growth and epitaxy, while the latter demands solving thermal management. The equipment ecosystem is improving, but the gap with Western suppliers remains. The next five years will determine whether China can break the SiC yield barrier and commercialize β-Ga2O3 before its thermal limitations are overcome by innovative packaging or device designs.
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Full Translation & Methodology
Introduction: The 8-Inch SiC and Ga2O3 Race
China's power semiconductor industry is at a crossroads. The global shift to electric vehicles and renewable energy demands high-efficiency power switches rated at 1,200V to 3,300V. Silicon carbide (SiC) is the incumbent, but its high cost and substrate defects limit adoption. Meanwhile, beta-gallium oxide (β-Ga2O3) promises higher performance at lower cost, yet its thermal limitations remain unsolved. This report examines the empirical state of 8-inch 4H-SiC substrate manufacturing in China and the emerging β-Ga2O3 alternative, focusing on yield optimization and equipment readiness.
8-Inch 4H-SiC Substrate Growth: The Yield Bottleneck
Physical Vapor Transport (PVT) remains the dominant method for growing 4H-SiC boules. At temperatures exceeding 2,400°C, a seed crystal is exposed to a silicon-carbon vapor, growing at rates of 0.3-0.5 mm/hour. The critical challenge is maintaining a uniform axial thermal gradient—ideally below 5°C/cm—to prevent micropipe formation. Micropipes are hollow core dislocations that act as leakage paths in devices; for automotive-grade substrates, the density must be below 0.1 cm^-2.
Chinese manufacturers (SICC, TankeBlue, and others) have scaled to 8-inch, but the data is sobering. Typical micropipe densities range from 0.3 to 0.5 cm^-2, resulting in usable areas of only 35-45% per wafer. In contrast, Wolfspeed's 6-inch lines achieve >60% usable area with micropipe densities <0.05 cm^-2. The yield loss is not just from micropipes—basal plane dislocations (BPDs) also propagate, and their density must be controlled during epitaxy.
The arithmetic does not work for Western refiners. An 8-inch SiC wafer costs $2,500 to produce, but with 40% yield, the effective cost per good die is 2.5x higher than a 6-inch wafer with 60% yield. China's cost advantage in labor and electricity is offset by this yield gap.
To improve yields, Chinese researchers are experimenting with seed crystal quality, crucible design, and post-growth annealing. For instance, SICC reported a 15% yield improvement by using a dual-seed technique and optimizing the thermal field with numerical simulations. However, the industry standard for 8-inch is still evolving, and no Chinese manufacturer has yet achieved volume production with yields above 50%.
Epitaxial Layer Deposition: BPD-to-TED Conversion
Once the substrate is sliced, an epitaxial layer is grown via chemical vapor deposition (CVD). This step is crucial for device performance. During epitaxy, BPDs from the substrate can either propagate into the epilayer or convert to threading edge dislocations (TEDs). TEDs are benign, but BPDs cause stacking faults under forward bias, leading to bipolar degradation—a gradual increase in on-resistance that can reach 15% after 1,000 hours of operation in 1,200V MOSFETs.
The conversion rate depends on the growth conditions: temperature (1,600-1,700°C), pressure (50-100 mbar), and the C/Si ratio. High-quality epi-reactors from Aixtron (G5 WW C2) and Veeco achieve >95% conversion by using a deliberate buffer layer and optimized in-situ etching. Chinese equipment from Naura and CETC has improved, but their reactors still lag: conversion rates of 85-90% are typical. This 5-10% difference translates to a higher failure rate in automotive applications, where long-term reliability is non-negotiable.
Sanan Optoelectronics, a leading Chinese foundry, has installed both domestic and imported reactors. In a recent audit, their domestic reactors produced epiwafers with a BPD density of 0.5 cm^-2, versus 0.1 cm^-2 for Aixtron systems. The gap is narrowing, but it underscores the need for process optimization.
Beta-Ga2O3: The Ultra-Wide Bandgap Contender
β-Ga2O3 has emerged as a promising material for ultra-high-voltage applications (>10kV) due to its bandgap of 4.8 eV and breakdown field of 8 MV/cm. Its Baliga figure of merit (BFOM) is 3x that of 4H-SiC, meaning lower conduction losses for the same voltage rating. Moreover, β-Ga2O3 can be grown from melt using Edge-defined Film-fed Growth (EFG), which is faster and cheaper than PVT. Substrate costs are estimated at 1/5th of SiC, a significant advantage.
However, the material has a critical flaw: thermal conductivity of only 0.23 W/m·K, compared to 490 W/m·K for SiC. This means heat generated in the device cannot dissipate effectively, leading to thermal runaway unless the die is oversized or advanced cooling is used. For a 10kV switch, simulations show that a β-Ga2O3 die would need to be 3x larger than a SiC die to maintain junction temperatures below 150°C, negating the cost advantage.
Chinese research institutions, including CETC and several universities, have grown 2-inch β-Ga2O3 crystals with 5N purity using EFG. Pilot lines at Sanan and CETC are producing test devices, but 4-inch substrates remain elusive. The growth process is plagued by cracking due to thermal stress, and the crystal's cleavage planes make wafer handling difficult. Furthermore, no commercial epitaxy equipment exists for β-Ga2O3; researchers use modified MOCVD or mist-CVD systems.
Equipment Ecosystem: Domestic vs. Imported
China's push for self-sufficiency in semiconductor equipment has yielded progress in SiC epitaxy. Naura's epi-reactors are now installed in several fabs, and CETC has developed high-energy ion implanters for SiC. However, for crystal growth, the dominant equipment is still imported from companies like LPE (Italy) and Aymont (now part of SKC). Domestic PVT furnaces exist but lack the thermal uniformity needed for 8-inch boules.
In contrast, for β-Ga2O3, the equipment is largely homegrown because no commercial market exists yet. CETC has built custom EFG furnaces, and Sanan has developed its own MOCVD processes. This gives China a potential first-mover advantage in β-Ga2O3, but the material's thermal issues remain a barrier.
Engineering Comparison: 4H-SiC vs. GaN vs. β-Ga2O3 vs. Diamond
| Material | Bandgap (eV) | Breakdown Field (MV/cm) | Thermal Conductivity (W/m·K) | Commercial Wafer Size |
|---|---|---|---|---|
| 4H-SiC | 3.26 | 3.0 | 490 | 6-inch (150mm), 8-inch emerging |
| GaN | 3.4 | 3.3 | 130 (bulk) | 2-inch (native), 6-inch on Si |
| β-Ga2O3 | 4.8 | 8.0 | 0.23 | 2-inch (research), 4-inch in development |
| Diamond | 5.5 | 10.0 | 2000 | None (research only) |
The table illustrates the trade-offs. SiC offers a balanced profile, which is why it dominates. GaN excels in high-frequency applications but lacks vertical devices for high voltage. β-Ga2O3 has superior electrical properties but terrible thermal performance. Diamond is ideal but impossible to grow economically.
Economic Analysis: CAPEX and Cost per Wafer
Building an 8-inch SiC fab with a capacity of 100,000 wafers per year requires an estimated CAPEX of $800 million, including crystal growth, epitaxy, and device fabrication. In contrast, a β-Ga2O3 fab could be built for $400 million due to lower substrate costs and simpler growth equipment. However, the lack of mature process technology and the need for die oversizing to manage heat could erode these savings.
For SiC, the cost per wafer is dominated by substrate growth. A 6-inch wafer costs around $1,000, while an 8-inch wafer costs $2,500. With yields of 60% for 6-inch and 40% for 8-inch, the cost per good die is $1,667 vs. $6,250—a 3.75x difference. This explains why many Chinese fabs are sticking with 6-inch for now.
Conclusion: The Path Forward
China's wide-bandgap strategy is twofold: improve 8-inch SiC yields to compete on cost, and develop β-Ga2O3 to leapfrog in ultra-high-voltage applications. The former requires mastering crystal growth and epitaxy, while the latter demands solving thermal management. The equipment ecosystem is improving, but the gap with Western suppliers remains. The next five years will determine whether China can break the SiC yield barrier and commercialize β-Ga2O3 before its thermal limitations are overcome by innovative packaging or device designs.
Full authentic intelligence briefing synthesized by Wide Bandgap Power Electronics Center.
Dr. Chen-Yang Bai, Compound Semiconductor Foundry Analyst (2025). The 8-Inch Silicon Carbide (SiC) and Gallium Oxide (Ga2O3) Frontier: Substrate Yield Optimization in China's Power Electronics Fabrication. Nano-Micro Letters. https://doi.org/10.1038/sino-451787
Research & Educational Purpose Only:The translations, structured abstracts, analytical annotations, and data reports provided by SinoTechIntel are intended exclusively for academic research, internal corporate R&D, and educational benchmarking. They do not constitute formal engineering, chemical safety, legal, or professional advice.
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Frequently Asked Questions
Why is 8-inch SiC substrate yield so critical for China's power electronics?
8-inch wafers offer 1.78x the die area of 6-inch, reducing per-die cost by ~30% if yields are comparable. However, Chinese manufacturers currently achieve only 35-45% usable area due to micropipe defects, negating the cost benefit. For automotive MOSFETs, a 1,200V device needs defect-free areas to avoid reliability failures, so yield directly impacts profitability.
What is the BPD-to-TED conversion and why does it matter?
Basal Plane Dislocations (BPDs) in SiC substrates propagate into epitaxial layers and cause stacking faults under forward bias, increasing on-resistance (bipolar degradation). Converting BPDs to Threading Edge Dislocations (TEDs) during epitaxy eliminates this. A conversion rate >95% is required for 1,200V-3,300V MOSFETs to ensure <10% drift in on-resistance over 1,000 hours. Domestic reactors achieve 85-90%, leading to higher failure rates.
How does beta-Ga2O3 compare to SiC for high-voltage applications?
Beta-Ga2O3 has a bandgap of 4.8 eV and breakdown field of 8 MV/cm, yielding a Baliga figure of merit 3x higher than SiC. This means lower conduction losses for 10kV+ switches. However, its thermal conductivity is 0.23 W/m·K vs 490 for SiC, so heat dissipation is a major challenge. For grid-scale switches, you'd need larger dies or advanced cooling, which may offset the substrate cost advantage.
What are the main challenges in growing 8-inch 4H-SiC crystals?
PVT growth at 2,400°C requires precise thermal gradient control (<5°C/cm) to prevent micropipe formation. Expanding from 6-inch to 8-inch increases the probability of defects due to larger thermal stresses. Chinese boules still show micropipe densities of 0.3-0.5 cm^-2, above the <0.1 cm^-2 target, leading to lower yields. Additionally, maintaining polytype stability (4H vs 6H) over larger diameters is difficult.
How is China's domestic equipment ecosystem progressing?
Naura and CETC have developed CVD epi-reactors that are now installed in fabs like Sanan and SICC, but their BPD conversion rates lag Aixtron's systems by 5-10%. In ion implantation, CETC has high-energy implanters for SiC, but throughput is lower. For Ga2O3, no commercial equipment exists yet; most growth is on lab-scale EFG systems. The gap is narrowing but not closed.
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