Key Takeaways & Executive Findings
- •• Fractional-N PLLs face jitter degradation from quantization error (Q-error), which induces quantization noise and fractional spurs, especially with wide loop bandwidths. • PFD-CP PLLs with offset PFD-CP and MASH DSM achieve low jitter but require large CP currents and loop filter capacitors, limiting power efficiency. • Multipath feedback technology compensates Q-error in the charge domain, reducing quantization noise and enabling high FoM with a dual-core class-F-1 VCO. • High-gain sampling PDs (e.g., sub-sampling PD) allow small CP currents and compact loop filters, but require DTC/DAC linearization to suppress spurs and noise folding.
Abstract
Fractional-N phase-locked loops (PLLs) are widely deployed in high-speed communication systems to generate local oscillator (LO) or clock signals with precise frequency. To support sophisticated modulations for increasing the data rate, the PLL needs to generate low-jitter output. Since the output frequency of the fractional-N PLL is not an integer multiple of the reference clock frequency, the phase error seen by the phase detector (PD) contains not only a random part induced by the oscillator and loop noise, but also a deterministic part due to the fractional operation, which is referred to as the quantization error (Q-error). The Q-error has two side effects on the output jitter. Firstly, the Q-error will induce quantization noise in the PLL output. Although the energy of quantization noise can be shaped to high offset frequencies and suppressed by the low-pass characteristics of the loop with the aid of a delta-sigma modulator (DSM), it could still contribute a substantial portion of the output jitter if a moderate or large loop bandwidth is required to suppress the oscillator's phase noise (PN). Secondly, when the Q-error passes through a nonlinear PD, fractional spurs will be generated, and quantization noise at high offset frequencies will be folded into in-band, which also degrades the output jitter. These side effects could limit the jitter performance in fractional-N PLLs. In the following sections, recent techniques to minimize the side effects of Q-error that enable low-jitter fractional-N PLL with high power efficiency will be reviewed.
1. Introduction
Fractional-N phase-locked loops (PLLs) are widely deployed in high-speed communication systems to generate local oscillator (LO) or clock signals with precise frequency. To support sophisticated modulations for increasing the data rate, the PLL needs to generate low-jitter output. Since the output frequency of the fractional-N PLL is not an integer multiple of the reference clock frequency, the phase error seen by the phase detector (PD) contains not only a random part induced by the oscillator and loop noise, but also a deterministic part due to the fractional operation, which is referred to as the quantization error (Q-error).
The Q-error has two side effects on the output jitter. Firstly, the Q-error will induce quantization noise in the PLL output. Although the energy of quantization noise can be shaped to high offset frequencies and suppressed by the low-pass characteristics of the loop with the aid of a delta-sigma modulator (DSM), it could still contribute a substantial portion of the output jitter if a moderate or large loop bandwidth is required to suppress the oscillator's phase noise (PN). Secondly, when the Q-error passes through a nonlinear PD, fractional spurs will be generated, and quantization noise at high offset frequencies will be folded into in-band, which also degrades the output jitter. These side effects could limit the jitter performance in fractional-N PLLs. In the following sections, recent techniques to minimize the side effects of Q-error that enable low-jitter fractional-N PLL with high power efficiency will be reviewed.
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Jun Yin, Haoran Li, Xiaoqi Lin, Rui P. Martins, Pui-In Mak (2025). Progress and Trends of Low-Jitter Fractional-N Phase-Locked Loops. Journal of Semiconductors (半导体学报 - 中国科学院半导体研究所). https://doi.org/10.1088/1674-4926/25040035
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Frequently Asked Questions
What is the main challenge in fractional-N PLLs for achieving low jitter?
The main challenge is the quantization error (Q-error) introduced by the fractional frequency division, which causes quantization noise and fractional spurs, degrading output jitter, especially when wide loop bandwidth is needed to suppress oscillator phase noise.
How does multipath feedback technology reduce quantization noise in PLLs?
Multipath feedback generates multiple feedback clocks with time spacing of one oscillator period and selects them based on DSM-predicted Q-error, using binary-scaled charge pumps to cancel quantization noise, thereby reducing its power by a factor of P.
What are the advantages of high-gain sampling PDs over traditional PFD-CP?
High-gain sampling PDs (e.g., sub-sampling PD) provide higher phase-to-voltage gain, allowing smaller charge pump currents and compact loop filters, while suppressing in-band noise from the PD and CP, improving power efficiency.
What is the role of DTC or DAC in high-gain PD PLLs?
DTC or DAC are used to compensate the Q-error to keep the phase error within the linear range of the high-gain PD. They must be designed with low noise and high linearity to avoid introducing additional jitter and spurs.
What is the significance of the reported PLL in 22-nm CMOS?
The PLL in 22-nm CMOS achieves a fractional spur of -64.8 dBc and RMS jitter of 37.7 fs at 9.44 GHz output, with a figure-of-merit (FoM) of -254.6 dB, which is among the highest reported for fractional-N PLLs, demonstrating the effectiveness of the proposed techniques.
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