A Novel Split Gate and Contact-Field-Plate LDMOS with Enhanced BV-Ron,sp Trade-off and Improved FOM

Abstract

To improve the breakdown voltage (BV)-specific on-resistance (Ron,sp) trade-off and enhance manufacturability, this article proposes a novel lateral diffused metal-oxide-semiconductor (LDMOS) structure that features a split gate and split contact field plate (CFP). This novel structure requires no additional bias voltages, masks, or process steps, making it fully compatible with the bipolar-CMOS-DMOS (BCD) process flow. The physical mechanisms are elucidated through technology computer-aided design (TCAD) simulations. In the on-state, the positively biased split gate forms an accumulation layer at the drift region surface, thereby reducing Ron,sp. In the off-state, both the split gate and split CFP introduce additional electric-field peaks that smooth the lateral electric field, thus preserving a high BV. Compared with the conventional CFP-LDMOS, the proposed CFP-LDMOS achieves an 8.52% reduction in Ron,sp without compromising BV, leading to an 8.07% improvement in the figure of merit (FOM). Notably, the proposed structure can be extended to LDMOS devices across different voltage levels within BCD platforms, demonstrating its broad applicability.

1. Introduction

In recent years, rapid developments in the field of automotive electronics and power management integrated circuits (PMIC) have generated growing interest in lateral diffused metal-oxide-semiconductor (LDMOS) transistors, owing to their high-voltage tolerance, low power consumption, and compatibility with conventional CMOS processes. However, the trade-off between specific on-resistance (Ron,sp) and breakdown voltage (BV) remains a major challenge in LDMOS performance optimization.

Implementing a field plate (FP) in LDMOS is an effective strategy for enhancing BV while reducing Ron,sp. This improvement is primarily attributed to three mechanisms: the extension of the depletion region, the introduction of additional electric-field peaks, and the formation of an electron accumulation layer. Owing to its simple fabrication process and significant performance benefits, the FP technique has been widely adopted in low-voltage applications. Recent research has focused on developing novel FP structures to further optimize the BV-Ron,sp trade-off of LDMOS, including: (1) stepped FP, which modulates the electric-field distribution in the drift region by varying the field-oxide thickness; (2) split FP with positive bias, which introduces electric-field peaks and enhances electron accumulation through a positively biased field plate; (3) linear-potential FP, which enforces a quasi-linear potential profile along the surface of the drift region, resulting in a uniform electric field in the off-state and carrier accumulation in the on-state, typically implemented through multi-layer metal designs or built-in integrated circuit (IC) control. However, these FP structures also have inherent limitations: (1) the stepped FP structure requires additional deposition and etching steps, substantially increasing process complexity and fabrication cost; (2) the split FP with positive bias may degrade BV and necessitate an additional voltage supply; (3) the linear-potential FP relies on multi-layer metal designs or built-in IC control, thereby increasing layout complexity and area consumption.