A Novel Split Gate and Contact-Field-Plate LDMOS with Enhanced BV-Ron,sp Trade-off and Improved FOM

• The proposed split gate and split contact field plate (CFP) LDMOS achieves an 8.52% reduction in specific on-resistance (Ron,sp) without compromising breakdown voltage (BV), leading to an 8.07% improvement in figure of merit (FOM). • The novel structure requires no additional bias voltages, masks, or process steps, ensuring full compatibility with standard BCD process flow and enhancing manufacturability. • TCAD simulations reveal that in the on-state, the positively biased split gate induces an accumulation layer at the drift region surface, reducing Ron,sp; in the off-state, the split gate and split CFP introduce additional electric-field peaks that smooth the lateral field, preserving high BV. • The proposed design is scalable across different voltage levels within BCD platforms, demonstrating broad applicability for power management integrated circuits.