Journal of Semiconductors (半导体学报 - 中国科学院半导体研究所)•2025
Authors: Bingrui Li, Zongnan Wang, Xiyuan Tang
High-precision analog-to-digital converters (ADCs) are fundamental components in modern electronic systems, bridging the physical analog world and digital intelligence. They find ubiquitous applications across diverse domains, ranging from the Internet of Things (IoT) to embodied artificial intelligence systems. Achieving high precision necessitates various circuit techniques including high-performance amplifiers and advanced calibration schemes. Furthermore, the evolution of ADC architectures has gradually elevated the significance of peripheral circuitry co-design in optimizing system-level performance metrics. In ISSCC 2025, several techniques are proposed to address these challenges. Amplifiers are typically the main bottleneck in the performance and efficiency of high-precision ADCs. The open-loop charge-transfer amplifier is a promising candidate for its good efficiency. However, conventional ones suffer from poor power supply rejection ratio (PSRR) and common-mode rejection, leading to signal-to-noise ratio (SNR) and robustness challenges. To overcome these problems, Huang et al. proposed a floating charge transfer topology, where the transistors are powered by a floating capacitor. As input and output currents of the capacitor are forced to be equal, supply noise will be forced to circulate within the amplifier. The post-layout simulation shows that the gain variation is limited to ±2.7% over process-voltage-temperature (PVT) variations without any trimming. Fabrication-induced variations, such as inter-stage gain errors and capacitor mismatches, can degrade ADC performance. Researches presented several improvements in dynamic element matching (DEM) and calibration techniques this year to address these challenges. Zhao et al. implemented a 120 dB SNDR 189 dB Schreier FoMs noise-shaping (NS) successive approximation register (SAR) ADC with hybrid mismatch shaping and system-level chopping. The 8b capacitor digital-to-analog converter (CDAC) is segmented into 3 most significant bits (MSBs) with 8 equal capacitors and 5 binary-weighted least significant bits (LSBs). Data weighted averaging (DWA) and mismatch error shaping (MES) are applied to the MSBs and LSBs respectively, increasing the quantizer resolution effectively. System-level chopping is adopted to eliminate the offset, 1/f noise, and the VCM induced CDAC nonlinearity simultaneously. In Ref. [4], Gao et al. extended the MES to multi-stage applications and presented a 93.3 dB-SNDR 180.4 dB-FoMs calibration-free NS pipelined-SAR ADC with cross-stage gain-mismatch-error-shaping technique. An extra capacitor CFB is added in the 1st-stage CDAC to serve as the mismatch reference of the 2nd-stage CDAC and residue amplifier. By involving CFB in the MES procedure of the 1st stage, both the capacitor mismatch of two stages and the gain error can be shaped and eliminated. This work further solved the MES saturation problem by pre-comparison during sampling. Sampling noise is a critical problem for discrete-time (DT) ADCs. Wang et al. proposed a single-amplification-based kT/C noise cancellation technique, and implemented a 92.5dB-SNDR 184.8dB-FoMs incremental NS pipeline ADC with a dither-based background gain error calibration scheme. In the design, single amplifier is used for the multi-cycle kT/C noise-cancelled conversion. This is enabled by moving the noise-cancellation amplifier out of the noise-shaping loop and utilizing dual CNC in a ping-pong fashion. By injecting dither in both sampling and residue amplification phases, the calibration engine can expand the kT/C noise-limited SNR beyond 100 dB with only 0.8 pF sampling capacitance. Another technique to solve the gain error problem is proposed in Ref. [6]. Chen et al. exploited the metastability and proposed a fast and robust background calibration technique in a 79.4dB-SNDR 176.3dB-FoMs pipelined-SAR ADC. This work adopts an improved version of the opportunistic PN-injection-based calibration. By monitoring the probability of metastability and adjusting the comparator delay, the metastability can be better controlled, leading to fast and robust calibration without affecting ADC’s normal conversion. In addition, the offset is cancelled by equalizing the likelihood of the second-stage MSB resolving to 1 or 0. ADCs are not standalone blocks—their peripheral circuits, together with the ADC core, have a significant impact on system-level performance. ISSCC 2025 showcased some pioneering co-design architecture that optimize ADC cores alongside peripheral circuits including input buffers and filters. In Ref. [8], Luan et al. focused on the input stage and proposed a gain-embedded bootstrapped sampler. The sampler is a PMOS transistor whose gate and drain are connected to the feedback signal through two CDACs. The input signal connects to the source, making the transistor work as a Gm cell. Since the sampler only draws a small current that relates to the residue signal, the driving requirements are relaxed. In addition, this structure also features lower sampling noise, good linearity and weaker kickback. In Ref. [9], Ye et al. proposed a continuous-time correlated level shifting (CLS) technique that realized a rail-to-rail high-linearity input buffer. An extra CLS capacitor and level shift phase are added compared to conventional CLS. After sampling the coarse version of input, the two CLS capacitors are connected in series at the output of the amplifier one by one. Therefore, the output swing can be extended and the equivalent open-loop gain can be boosted at the end of the second level shift phase, leading to a rail-to-rail linear operation. In Ref. [6], Chen et al. also put efforts into the innovation of the input buffer and proposed a split coarse-fine input-buffer-sampling scheme. The input buffer is split into a low-power push−pull source follower as the coarse buffer and a high-power cascoded one as the fine buffer. During sampling, the coarse buffer first charges its loading capacitor CS,C to a value close to the input signal, and then, the input directly connects to CS,C, resulting in a small differential voltage to the fine buffer. Finally, a coarse ADC quantizes and [truncated]