Key Takeaways & Executive Findings
- •• Process optimizations in film sputtering and pre-deposition treatment improved within-wafer resistance uniformity from 11% to 8% and reduced inter-wafer variation from 23% to below 6%. • The yield of 8 Mb embedded RRAM products increased from 87% to 98.5% through systematic process improvements. • The RRAM achieved a fast read speed of 4.8 ns, read disturb immunity of 3×10^8 cycles at 95°C, endurance of 10^3 cycles for 1 Mb cells, and data retention of 12.5 years at 125°C. • Post-HTOL testing confirmed stable high/low resistance window, validating the reliability assurance framework for mass production.
Abstract
To address the challenges of complexity, power consumption, and cost constraints in traditional display driver integrated circuits (DDICs) caused by external NOR Flash and SRAM, this work proposes an embedded resistive random-access memory (RRAM) integration solution based on a 40 nm high-voltage CMOS logic platform. Targeting the yield fluctuations and stability challenges during RRAM mass production, systematic process optimizations are implemented to achieve synergistic improvements in RRAM performance and yield. Through modifications to the film sputtering and pre-deposition treatment, the within-wafer resistance uniformity (RSU) of the oxygen-deficient layer (ODL) thin film is improved from 11% to 8%, while inter-wafer process stability variation reduces from 23% to below 6%. Consequently, the yield of 8 Mb RRAM embedded mass production products increases from 87% to 98.5%. In terms of device performance, the RRAM demonstrates a fast 4.8 ns read speed, exceptional read disturb immunity of 3 × 108 cycles at 95 °C, 103 write/erase endurance cycles for the 1 Mb cells, and data retention of 12.5 years at 125 °C. Post high-temperature operating life (HTOL) testing exhibits stable high/low resistance window. This study provides process optimization strategies and a reliability assurance framework for the mass production of highly integrated, low-power embedded RRAM display driver IC.
1. Introduction
Display driver integrated circuits (DDICs), as the core control units of modern display systems, determine the brightness, color, and dynamic response of display devices by precisely regulating the voltage or current of each pixel. Their applications have expanded from traditional liquid crystal displays (LCDs) to advanced technologies such as active-matrix organic light-emitting diodes (AMOLEDs), micro light-emitting diodes (Micro-LEDs), and quantum-dot LEDs (QLEDs)[1−3]. Among these, OLEDs, dubbed the third-generation display technology, have the unique technical advantages of low energy consumption, high luminous efficiency, superior brightness, and slim form factors. They have recently gained widespread adoption in smartphones, wearable devices, laptops, and other smart terminals, showcasing significant market potential and commercial value[4].
In high-end displays like AMOLEDs, minor variations in manufacturing processes and material properties lead to deviations in pixel-level luminous efficiency, which can affect overall display quality. To address these challenges, embedded memory solutions are increasingly being integrated into DDICs to reduce system complexity, power consumption, and cost. This work proposes an embedded RRAM integration solution based on a 40 nm high-voltage CMOS logic platform, targeting yield fluctuations and stability challenges during mass production through systematic process optimizations.
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SUI Zhenchao, WU Yanqing, LV Zhichao, ZHANG Xing (2025). Synergistic performance and yield improvement of embedded RRAM product through process optimization in 40 nm CMOS platform. SinoTechIntel Verified Research. https://doi.org/10.1088/1674-4926/25100021
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Frequently Asked Questions
What is the main contribution of this paper?
The paper presents a systematic process optimization approach for embedded RRAM in a 40 nm CMOS platform, achieving significant improvements in both performance and yield, with yield increasing from 87% to 98.5% for 8 Mb products.
How was the yield improvement achieved?
Yield improvement was achieved through modifications to film sputtering and pre-deposition treatment, which improved within-wafer resistance uniformity from 11% to 8% and reduced inter-wafer variation from 23% to below 6%.
What are the key performance metrics of the RRAM?
The RRAM demonstrates a fast read speed of 4.8 ns, read disturb immunity of 3×10^8 cycles at 95°C, endurance of 10^3 cycles for 1 Mb cells, and data retention of 12.5 years at 125°C.
What is the significance of this work for display driver ICs?
This work provides a viable embedded RRAM solution for display driver ICs, reducing reliance on external NOR Flash and SRAM, thereby lowering complexity, power consumption, and cost while maintaining high reliability.
What reliability testing was performed?
High-temperature operating life (HTOL) testing was performed, and the RRAM exhibited stable high/low resistance window post-testing, confirming its reliability for mass production.
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