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Open AccessDOI: 10.1088/1674-4926/26020058Original Research

A transferable route to two-dimensional gate-all-around electronics

Jian Wang¹,Ruiqin Wu¹,Jianfeng Jiang¹

Key Laboratory for the Physics and Chemistry of Nanodevices and Center for Carbon-based Electronics, School of Electronics, Peking University, Beijing 100871, China

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Academic Research Journal
Published:January 15, 2026Edition:Vol. 32, Issue 2 • pp. 100-112Citation:Jian Wang et al. (2026), Academic Research Journal
Impact FactorPeer-Reviewed Core
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Key Takeaways & Executive Findings

  • • A novel buffered van der Waals epitaxy technique enables wafer-scale synthesis of single-crystalline 2D GAA heterostructures. • The pre-deposited α-Bi2SeO5 buffer oxide effectively mitigates lattice and symmetry mismatch, enabling uniform Bi2O2Se growth. • In situ controlled oxidation transforms the top layer into β-Bi2SeO5, forming a high-k dielectric/semiconductor/high-k dielectric sandwich with atomically clean interfaces. • This scalable method overcomes limitations of existing techniques, paving the way for industry-compatible 2D GAA electronics.
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Abstract

The relentless drive for miniaturization in microelectronics, guided by Moore's Law, is approaching a critical inflection point. Silicon-based transistors are confronting fundamental physical limits at the atomic scale, where issues of power leakage and degraded electrostatic control become increasingly severe. To sustain performance scaling, the semiconductor industry is transitioning to gate-all-around (GAA) nanosheet architectures for sub-2-nanometer technology nodes. A more revolutionary path lies in integrating atomically thin two-dimensional (2D) semiconductors as the channel material within these GAA structures. 2D semiconductors promise superior electrostatic gate control and lower power consumption, and their potential for monolithic three-dimensional integration is essential for extending computational capabilities. However, the grand challenge has been the absence of a scalable, industry-compatible method to synthesize high-quality, uniform 2D semiconductor channels that are seamlessly and conformally encapsulated by high-k gate dielectrics in a GAA configuration. Existing techniques are plagued by interfacial defects, poor uniformity, or intrinsic limitations in achieving dual-sided, wafer-scale integration. Confronting this challenge, a groundbreaking study by Peng et al. reports the wafer-scale, uniform synthesis of single-crystalline 2D high-k dielectric/semiconductor/high-k dielectric GAA heterostructures via an innovative buffered van der Waals epitaxy technique. The core innovation lies in the pre-deposition of a high-k van der Waals buffer oxide (α-Bi2SeO5) on an industry-standard r-plane sapphire substrate. This buffer oxide mitigates the lattice and symmetry mismatch between the substrate and the target 2D semiconductor (Bi2O2Se), enabling epitaxial growth of a uniform, single-crystalline film. Through controlled oxidation, the top layer of Bi2O2Se is transformed into another high-k dielectric (β-Bi2SeO5), forming the sandwich-like GAA heterostructure (β-Bi2SeO5/Bi2O2Se/α-Bi2SeO5) in a single, scalable growth run with atomically sharp interfaces. Comprehensive characterization confirms exceptional uniformity and crystalline quality over 2-inch wafers.

1. Introduction

The relentless drive for miniaturization in microelectronics, guided by Moore's Law, is approaching a critical inflection point. Silicon-based transistors, the workhorse of modern computing, are confronting fundamental physical limits at the atomic scale, where issues of power leakage and degraded electrostatic control become increasingly severe[1]. To sustain the trajectory of performance scaling, the semiconductor industry is transitioning to gate-all-around (GAA) nanosheet architectures for sub-2-nanometer technology nodes[2]. Yet, this represents only an incremental evolution for silicon.

A more revolutionary path lies in integrating atomically thin two-dimensional (2D) semiconductors as the channel material within these GAA structures[3]. 2D semiconductors, with their atomic thickness, promise superior electrostatic gate control and lower power consumption. Their potential for monolithic three-dimensional (3D) integration is essential for extending computational capabilities beyond the limits of traditional silicon scaling[4]. However, the grand challenge has been the absence of a scalable, industry-compatible method to synthesize high-quality, uniform 2D semiconductor channels that are seamlessly and conformally encapsulated by high-k gate dielectrics in a GAA configuration. Existing techniques, such as direct deposition of amorphous oxides on 2D materials[5] or mechanical assembly of van der Waals (vdW) heterostructures[6], are plagued by interfacial defects, poor uniformity, or intrinsic limitations in achieving dual-sided, wafer-scale integration. Therefore, the scalable preparation of single-crystalline 2D GAA heterostructures with atomically clean interfaces stands as a pivotal bottleneck for the future of electronics.

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Jian Wang, Ruiqin Wu, Jianfeng Jiang (2026). A transferable route to two-dimensional gate-all-around electronics. SinoTechIntel Verified Research. https://doi.org/10.1088/1674-4926/26020058
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Frequently Asked Questions

What is the main innovation of this research?

The main innovation is the development of a buffered van der Waals epitaxy technique that enables wafer-scale synthesis of single-crystalline 2D gate-all-around heterostructures with atomically clean interfaces, using a high-k buffer oxide to mitigate lattice mismatch and in situ oxidation to form the dielectric layers.

How does the buffered van der Waals epitaxy technique work?

The technique pre-deposits a high-k van der Waals buffer oxide (α-Bi2SeO5) on a sapphire substrate, which mitigates lattice and symmetry mismatch. This allows epitaxial growth of a uniform Bi2O2Se film. Then, controlled oxidation transforms the top layer into β-Bi2SeO5, forming a sandwich structure of high-k dielectric/semiconductor/high-k dielectric.

What are the advantages of using 2D semiconductors in GAA transistors?

2D semiconductors offer atomic thickness, which provides superior electrostatic gate control and lower power consumption. They also enable monolithic 3D integration, extending computational capabilities beyond traditional silicon scaling limits.

What challenges does this research address?

It addresses the lack of scalable, industry-compatible methods to synthesize high-quality, uniform 2D semiconductor channels with conformal high-k dielectric encapsulation in a GAA configuration, overcoming issues like interfacial defects and poor uniformity in existing techniques.

What is the significance of the atomically clean interfaces?

Atomically clean interfaces are crucial for reducing carrier scattering and improving device performance. They ensure high carrier mobility and reliable operation, which are essential for advanced electronic devices.

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