Key Takeaways & Executive Findings
- •• Floating charge-transfer amplifier topology improves PSRR and common-mode rejection, achieving ±2.7% gain variation over PVT without trimming. • Hybrid mismatch shaping (DWA+MES) and system-level chopping enable a 120 dB SNDR, 189 dB FoMs NS-SAR ADC. • Cross-stage gain-mismatch-error-shaping technique achieves calibration-free NS pipelined-SAR ADC with 93.3 dB SNDR and 180.4 dB FoMs. • Pre-comparison during sampling solves MES saturation, enhancing robustness of high-precision ADCs.
Abstract
High-precision analog-to-digital converters (ADCs) serve as fundamental components in modern electronic systems, bridging the physical analog world and digital intelligence. They find ubiquitous applications across diverse domains, ranging from the Internet of Things (IoT) to embodied artificial intelligence systems. Achieving high precision necessitates various circuit techniques including high-performance amplifiers and advanced calibration schemes. Furthermore, the evolution of ADC architectures has gradually elevated the significance of peripheral circuitry co-design in optimizing system-level performance metrics. In ISSCC 2025, several techniques are proposed to address these challenges. Amplifiers are typically the main bottleneck in the performance and efficiency of high-precision ADCs. The open-loop charge-transfer amplifier is a promising candidate for its good efficiency. However, conventional ones suffer from poor power supply rejection ratio (PSRR) and common-mode rejection, leading to signal-to-noise ratio (SNR) and robustness challenges. To overcome these problems, Huang et al. proposed a floating charge transfer topology, where the transistors are powered by a floating capacitor. As input and output currents of the capacitor are forced to be equal, supply noise will be forced to circulate within the amplifier. The post-layout simulation shows that the gain variation is limited to ±2.7% over process-voltage-temperature (PVT) variations without any trimming. Fabrication-induced variations, such as inter-stage gain errors and capacitor mismatches, can degrade ADC performance. Researches presented several improvements in dynamic element matching (DEM) and calibration techniques this year to address these challenges. Zhao et al. implemented a 120 dB signal-to-noise-and-distortion ratio (SNDR) 189 dB Schreier figure-of-merit (FoMs) noise-shaping (NS) successive approximation register (SAR) ADC with hybrid mismatch shaping and system-level chopping. The 8b capacitor digital-to-analog converter (CDAC) is segmented into 3 most significant bits (MSBs) with 8 equal capacitors and 5 binary-weighted least significant bits (LSBs). Data weighted averaging (DWA) and mismatch error shaping (MES) are applied to the MSBs and LSBs respectively, increasing the quantizer resolution effectively. System-level chopping is adopted to eliminate the offset, 1/f noise, and the VCM induced CDAC nonlinearity simultaneously. In Ref. [4], Gao et al. extended the MES to multi-stage applications and presented a 93.3 dB-SNDR 180.4 dB-FoMs calibration-free NS pipelined-SAR ADC with cross-stage gain-mismatch-error-shaping technique. An extra capacitor CFB is added in the 1st-stage CDAC to serve as the mismatch reference of the 2nd-stage CDAC and residue amplifier. By involving CFB in the MES procedure of the 1st stage, both the capacitor mismatch of two stages and the gain error can be shaped and eliminated. This work further solved the MES saturation problem by pre-comparison during sampling. Sampling noise is a critical problem for discrete-time (DT) ADCs. Wang et al. propose...
1. Introduction
High-precision analog-to-digital converters (ADCs) serve as fundamental components in modern electronic systems, bridging the physical analog world and digital intelligence. They find ubiquitous applications across diverse domains, ranging from the Internet of Things (IoT) to embodied artificial intelligence systems. Achieving high precision necessitates various circuit techniques including high-performance amplifiers and advanced calibration schemes. Furthermore, the evolution of ADC architectures has gradually elevated the significance of peripheral circuitry co-design in optimizing system-level performance metrics.
In ISSCC 2025, several techniques are proposed to address these challenges. Amplifiers are typically the main bottleneck in the performance and efficiency of high-precision ADCs. The open-loop charge-transfer amplifier is a promising candidate for its good efficiency. However, conventional ones suffer from poor power supply rejection ratio (PSRR) and common-mode rejection, leading to signal-to-noise ratio (SNR) and robustness challenges. To overcome these problems, Huang et al. proposed a floating charge transfer topology, where the transistors are powered by a floating capacitor. As input and output currents of the capacitor are forced to be equal, supply noise will be forced to circulate within the amplifier. The post-layout simulation shows that the gain variation is limited to ±2.7% over process-voltage-temperature (PVT) variations without any trimming.
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Bingrui Li, Zongnan Wang, Xiyuan Tang (2025). High-precision ADC design techniques in ISSCC 2025. SinoTechIntel Verified Research. https://doi.org/10.1088/1674-4926/25050012
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Frequently Asked Questions
What is the floating charge transfer amplifier technique?
It is a technique where transistors are powered by a floating capacitor, forcing supply noise to circulate within the amplifier, thereby improving PSRR and common-mode rejection. It achieves ±2.7% gain variation over PVT without trimming.
How does hybrid mismatch shaping improve ADC performance?
Hybrid mismatch shaping combines DWA for MSBs and MES for LSBs in a segmented CDAC, effectively increasing quantizer resolution and reducing capacitor mismatch errors, leading to higher SNDR and FoMs.
What is cross-stage gain-mismatch-error-shaping?
It is a technique that adds an extra capacitor in the first-stage CDAC to serve as a mismatch reference for the second stage, shaping both capacitor mismatch and gain error, enabling calibration-free operation in NS pipelined-SAR ADCs.
How is MES saturation solved?
MES saturation is solved by performing pre-comparison during the sampling phase, which prevents the shaping filter from overloading and ensures stable operation.
What are the key performance metrics of the ADCs presented?
The NS-SAR ADC achieves 120 dB SNDR and 189 dB FoMs, while the NS pipelined-SAR ADC achieves 93.3 dB SNDR and 180.4 dB FoMs, both demonstrating high precision and efficiency.
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