Two-Dimensional Materials, the Ultimate Solution for Future Electronics and Very-Large-Scale Integrated Circuits

Abstract

The relentless down-scaling of electronics grands the modern integrated circuits (ICs) with the high speed, low power dissipation and low cost, fulfilling diverse demands of modern life. Whereas, with the semiconductor industry entering into sub-10 nm technology nodes, degrading device performance and increasing power consumption give rise to insurmountable roadblocks confronted by modern ICs that need to be conquered to sustain the Moore law's life. Bulk semiconductors like prevalent Si are plagued by seriously degraded carrier mobility as thickness thinning down to sub-5 nm, which is imperative to maintain sufficient gate electrostatic controllability to combat the increasingly degraded short channel effects. Nowadays, the emergence of two-dimensional (2D) materials opens up new gateway to eschew the hurdles laid in front of the scaling trend of modern IC, mainly ascribed to their ultimately atomic thickness, capability to maintain carrier mobility with thickness thinning down, dangling-bonds free surface, wide bandgaps tunability and feasibility to constitute diverse heterostructures. Blossoming breakthroughs in discrete electronic device, such as contact engineering, dielectric integration and vigorous channel-length scaling, or large circuits arrays, as boosted yields, improved variations and full-functioned processor fabrication, based on 2D materials have been achieved nowadays, facilitating 2D materials to step under the spotlight of IC industry to be treated as the most potential future successor or complementary counterpart of incumbent Si to further sustain the down-scaling of modern IC.

1. Introduction

Since Gordon Moore proposed his famous Moore's law in 1965 [1], integrated circuits doubled every two years, manifesting by physical dimensions of discrete electronic device reducing by 0.7 times, ascribed to which the footprint reduces by ~0.5 times. On the contrary, operating speed doubles, power dissipation and cost both decrement by a factor of two [2, 3]. The Moore's law had been complied with integrated circuits (ICs) happily during the former several decades until semiconductor industry entered into sub-100 nm node, where gate began to give over part of its electrostatic dominance over channel to drain bias attributed to drain's stealing behavior over channel barrier [4, 5]. In this context, the notorious short channel effects (SCEs) began to come into view and draw themselves enormous attention to be dedicated efforts to [6].

The prominent SCEs that seriously degrade device performance comprise of subthreshold swing (SS), drain-induced barrier lower (DIBL), punch-through, Subthreshold-voltage (Vt) rolling off in accordance with channel length scaling and leakage current increasing [7–10]. SS describes the switching capability of the device and the smaller the SS, the stronger the gate electrostatic control over channel is, and DIBL is on behalf of the competing behavior of drain bias over the controllability of channel with regards to gate bias. Punch-through denotes the phenomenon of the depletion region induced by source and drain doping jointing with each other under the channel region, contributing to leakage current increment, while Vt rolling off contributes to leakage current escalating and stability issue in circuits, where leakage current increasing finally results in static power consumption surging.

The relentless downscaling of electronics poses imperative requests for novel device structures or ingenious materials which can reach a tradeoff between high discrete device performance and low power dissipation to sustain the Moore's law life further, this regime of semiconductor technology is termed as More Moore. For another, modern life brings forwards the requirements for 5G or 6G communication, cloud computing, artificial intelligent and neuromorphic computing, which all comes following the blossoming of More than Moore.