High-Performance Gate-All-Around Field Effect Transistors Based on Orderly Arrays of Catalytic Si Nanowire Channels

Abstract

Gate-all-around field-effect transistors (GAA-FETs) represent the leading-edge channel architecture for constructing state-of-the-art high-performance FETs. Despite the advantages offered by the GAA configuration, its application to catalytic silicon nanowire (SiNW) channels, known for facile low-temperature fabrication and high yield, has faced challenges primarily due to issues with precise positioning and alignment. In exploring this promising avenue, we employed an in-plane solid–liquid-solid (IPSLS) growth technique to batch-fabricate orderly arrays of ultrathin SiNWs, with diameters of DNW = 22.4 ± 2.4 nm and interwire spacing of 90 nm. An in situ channel-releasing technique has been developed to well preserve the geometry integrity of suspended SiNW arrays. By optimizing the source/drain contacts, high-performance GAA-FET devices have been successfully fabricated, based on these catalytic SiNW channels for the first time, yielding a high on/off current ratio of 10^7 and a steep subthreshold swing of 66 mV dec−1, closing the performance gap between the catalytic SiNW-FETs and state-of-the-art GAA-FETs fabricated by using advanced top-down EBL and EUV lithography. These results indicate that catalytic IPSLS SiNWs can also serve as the ideal 1D channels for scalable fabrication of high-performance GAA-FETs, well suited for monolithic 3D integrations.

1. Introduction

Gate-all-around field-effect transistors (GAA-FETs, as depicted in Fig. 1a), which offer exceptional electrostatic control, are becoming the mainstream device architecture for technology nodes < N3 nm [1–4], where ultrathin crystalline silicon nanowires (c-SiNWs) are considered as ideal quasi-one-dimensional (1D) channel materials to mitigate the short-channel effect in highly integrated CMOS logics. However, to implement monolithic 3D integration that enables higher integration density, it is essential to fabricate ultrathin SiNW channels on the stacked layers, where a monocrystalline Si wafer substrate is absent. Instead of using a conventional top-down etching procedure in the bottom logic layer, these 1D SiNW channels should be grown in precise locations as orderly arrays directly on the insulating dielectric layer, via a low-temperature process to avoid thermal damage to the underlying logic layers [5–7].

To address this challenge, a low-temperature catalytic growth of such SiNW channels provides an ideal option, as it doesn’t rely on the preexistence of c-Si wafer [8, 9]. Although the famous vapor–liquid-solid (VLS) growth mechanism has been widely exploited to produce high-quality SiNW channels for the demonstration of high-performance FETs and sensors [10–13], the vertical orientation of the VLS-grown SiNWs makes them difficult to integrate into the planar device architecture [14, 15]. Particularly, the post-growth transfer and release of individual VLS-SiNWs onto pre-defined electrode trench, for the subsequent formation of GAA-FET, lacks deterministic position and orientation control, and is thus technically incompatible with the standard planar manufacturing procedure [11, 16, 17]. In order to address this challenge, an in-plane solid–liquid-solid (IPSLS) mechanism [18–20] has been developed in our previous works, where indium (In) catalyst droplets absorb amorphous silicon (a-Si) precursor thin film to produce c-SiNWs along pre-defined guiding step edges. Indeed, a rather high-density integration of the IPSLS SiNWs has been demonstrated, under the guidance of terrace mini-steps [21, 22] or the sidewall grooves [23, 24], achieving an impressive diameter and uniformity control, backed by a series of tailored catalyst formation technologies [24, 25]. However, the performance of planar or GAA-FETs fabricated with catalytic SiNW channels still lags significantly behind that of state-of-the-art fin- or GAA gate FETs [11, 16, 17, 26]. Specifically, the subthreshold swing (SS) of the catalytic SiNW-FETs, a key indicator of the strength of electrostatic control, typically ranges from 850 to 100 mV dec−1 [27–33], which is still far from the theoretical limit of 60 mV dec−1. For the IPSLS SiNWs, a genuine GAA-FET has not yet been demonstrated, and their potential to serve as 1D channels for high-performance FETs remains to be explored and verified through direct experimental evidence.

In this work, we focus on demonstrating high-performance GAA-FETs based on orderly arrays of catalytic SiNW channels grown by IPSLS, achieving a high on/off current ratio of 10^7 and a steep subthreshold swing of 66 mV dec−1, thereby closing the performance gap with state-of-the-art GAA-FETs fabricated by advanced lithography.