Key Takeaways & Executive Findings
- •• A set of MoS2 nanosheet field-effect transistors (NSFETs) are fabricated, with two stacking nanosheet channel, in which two parallel MoS2 channels are controlled by three gate electrodes simultaneously. • By building a comprehensive framework, the feasibility of replacing silicon-based complementary field-effect transistors of 1 nm node with 2D-NSFETs provides a 2D technology solution for 1 nm nodes, i.e., "2D eq 1 nm" nodes are verified. • The horizontally miniaturized 2D-NSFET achieves a frequency increase of 28% at a fixed power consumption and also obtains a similar trend in 16-bit RISC-V CPU. • The ultra-scaled 2D-NSFET improves frequency by 36% at a fixed power consumption compared to Si-CFET with the same average device footprint, demonstrating potential for low-cost, high-performance next-generation transistors.
Abstract
Emerging two-dimensional (2D) semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness. As the stacking process advances, the complexity and cost of nanosheet field-effect transistors (NSFETs) and complementary FET (CFET) continue to rise. The 1 nm technology node is going to be based on Si-CFET process according to international roadmap for devices and systems (IRDS) (2022, https://irds.ieee.org/), but not publicly confirmed, indicating that more possibilities still exist. The miniaturization advantage of 2D semiconductors motivates us to explore their potential for reducing process costs while matching the performance of next-generation nodes in terms of area, power consumption and speed. In this study, a comprehensive framework is built. A set of MoS2 NSFETs were designed and fabricated to extract the key parameters and performances. And then for benchmarking, the sizes of 2D-NSFET are scaled to a extent that both of the Si-CFET and 2D-NSFET have the same average device footprint. Under these conditions, the frequency of ultra-scaled 2D-NSFET is found to improve by 36% at a fixed power consumption. This work verifies the feasibility of replacing silicon-based CFETs of 1 nm node with 2D-NSFETs and proposes a 2D technology solution for 1 nm nodes, i.e., "2D eq 1 nm" nodes. At the same time, thanks to the lower characteristic length of 2D semiconductors, the miniaturized 2D-NSFET achieves a 28% frequency increase at a fixed power consumption. Further, developing a standard cell library, these devices obtain a similar trend in 16-bit RISC-V CPUs. This work quantifies and highlights the advantages of 2D semiconductors in advanced nodes, offering new possibilities for the application of 2D semiconductors in high-speed and low-power integrated circuits.
1. Introduction
Semiconductor technology continues to evolve with silicon as the primary material. However, as feature sizes continue to shrink, traditional silicon-based field-effect transistors (FETs) are unable to maintain reliable and robust performance when channel lengths are reduced to less than 12 nm, due to short-channel effects (SCEs). As integration technology evolves to the 5 nm process node, increasing SCEs, reduced fin counts, weakened electrostatic control and increased fabrication complexity limit the miniaturization performance of FinFET devices [2–4]. In order to improve gate control for ultra-short channels and to ensure that sufficiently strong electrostatic control is constructed to meet the requirements of more advanced semiconductor processes, gate-all-around FETs (GAAFETs) have become the dominant device at the 5 nm and sub-5 nm nodes [5–7]. Nanosheet field-effect transistors (NSFETs) with the GAA structure have gained wide acceptance in the semiconductor industry for their excellent low power performance, enhanced ability to suppress SCEs, superior drive capability, lower parasitic capacitance, flexible channel size tunability and higher device reliability [8, 9]. Further, IMEC proposes new device structures such as Forksheet FET [10] and complementary FET (CFET) [11]. Due to their significant advantages in terms of power consumption, performance and area (PPA), CFETs have quickly emerged as a strong candidate for overcoming the forthcoming limitations in semiconductor device miniaturization and hold promise for applications beyond the 3 nm technology node (Fig. 1a). As the size continues to shrink, the underlying physical limitations that are difficult to completely resolve have prompted researchers to continue to explore other options.
Two-dimensional (2D) materials with their excellent semiconductor properties offer a new way to move beyond the limitations of silicon-based devices, potentially enabling further miniaturization while reducing process complexity and cost.
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Yang Shen, Zhejia Zhang, Zhujun Yao, Mengge Jin, Jintian Gao, Yuhan Zhao, Wenzhong Bao, Yabin Sun, He Tian (2025). A Valuable and Low-Budget Process Scheme of Equivalized 1 nm Technology Node Based on 2D Materials. Nano-Micro Letters. https://doi.org/10.1007/s40820-025-01702-7
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Frequently Asked Questions
What is the main contribution of this paper?
The paper proposes a low-budget process scheme for equivalized 1 nm technology node using 2D materials, demonstrating that 2D-NSFETs can replace Si-CFETs with improved frequency at fixed power consumption, verified through fabricated MoS2 NSFETs and simulations.
How do 2D-NSFETs compare to Si-CFETs in terms of performance?
When scaled to the same average device footprint, ultra-scaled 2D-NSFETs achieve a 36% frequency improvement at fixed power consumption compared to Si-CFETs, and a 28% increase in horizontally miniaturized devices, with similar trends in 16-bit RISC-V CPUs.
What are the key advantages of using 2D materials for 1 nm node transistors?
2D materials offer atomic-level thickness, better electrostatic control, reduced short-channel effects, and potential for lower fabrication complexity and cost, making them promising for next-generation nodes.
What is the '2D eq 1 nm' node concept?
It is a proposed 2D technology solution that equivalizes the performance of 1 nm silicon-based CFETs using 2D-NSFETs, providing a feasible alternative with lower process cost and complexity.
What experimental work was conducted in this study?
The authors fabricated a set of MoS2 NSFETs with two stacking nanosheet channels controlled by three gate electrodes, extracting key parameters to build a comprehensive framework for benchmarking against Si-CFETs.
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