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WSC optimizer: an optimization tool for wafer-scale chip architecture exploration

Authors: Wenbo ZHANG; Bo DING; Shuai WEI; Qinrang LIU; Hong YU; Ke SONG; Wei GUO; Bo MEI; Rui ZHENG

DOI: 10.1631/ENG_ITEE_2025_0008Status: Verified Translated Edition
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Key Findings in This Report

• Pioneers a systematic WSC architecture exploration framework integrating layout, mapping, and co-design into multi-objective optimization. • Introduces a hierarchical multi-objective collaborative optimization approach that jointly balances physical constraints and communication patterns. • Develops a WSC optimizer toolchain with mixed-granularity simulation, enabling automated generation of optimal configurations. • Reports up to 22× throughput improvement and 5× latency reduction for cryptographic and signal-processing workloads compared to traditional architectures.