WSC optimizer: an optimization tool for wafer-scale chip architecture exploration

Abstract

In recent years, mature advanced packaging technologies have increasingly enabled the integration of multiple small dies into larger chips, while retaining chip-scale density and high-bandwidth interconnects. To address the inefficiencies of manual design and the challenges of heterogeneous optimization in wafer-scale chip (WSC) development, we systematically explore key factors in WSC architecture design. We integrate chip layout, operator mapping, and hardware–software co-design, and formulate the WSC architecture exploration problem as a multi-objective optimization task. First, we establish a hierarchical architecture model for WSCs, unifying the quantification of core constraints and interconnect topology constraints; second, we propose a hierarchical multi-objective collaborative optimization framework to jointly optimize physical constraints and task mapping communication patterns; finally, we develop a WSC optimizer toolchain that supports mixed-granularity simulation and generates optimal configurations for representative workloads. Experimental results demonstrate that compared with traditional computer architectures, the optimized architectures generated by our WSC optimizer achieve up to a 22× throughput improvement and a 5× latency reduction in application domains, such as cryptographic decryption and signal processing.

1. Introduction

Recent years have seen the rapid development of technologies, such as large-scale language models (LLMs), resulting in an exponential growth in computational demand (Zhu et al., 2025). This trend is strikingly epitomized by the remarkable expansion in model parameters, which have escalated from millions in bidirectional encoder representations from Transformers (BERT) to a staggering 1.8 trillion in GPT-4, a growth of over a thousand times (Brown et al., 2020; Achiam et al., 2023; Chowdhery et al., 2023; Touvron et al., 2023; Yenduri et al., 2024). Concurrently, training costs have escalated dramatically. For instance, GPT-4 has up to 1.8 trillion parameters (Baktash and Dawodi, 2023; Patel and Wong, 2023). At a cloud cost of roughly $1 per hour using A100, the training cost for a single run would amount to approximately $63 million (Patel and Wong, 2023). This growth trend is expected to continue, as large models continue to demonstrate superior performance in natural language understanding and content generation tasks (Raffel et al., 2020; Zhang SS et al., 2022; Baktash and Dawodi, 2023).

As microelectronics manufacturing technology approaches fundamental physical limits (IEEE, 2024), traditional single-chip integration faces significant size constraints, leading to reduced yields and increased costs (Bohr, 2009; Han et al., 2024). To address these challenges, the wafer-scale chip (WSC) (Burns et al., 2006) has emerged as a promising solution. This technology leverages advanced packaging and innovative chiplet design methods to integrate numerous processing cores within a single package (Shao et al., 2019), thereby enhancing computational density and intercommunication bandwidth. Furthermore, WSC offers a high degree of design flexibility, allowing customization of functional modules based on specific application requirements. This ensures an optimal balance between cost-effectiveness and manufacturing efficiency, while preserving superior performance.

Meanwhile, as microelectronic fabrication technology approaches the fundamental 1-nm physical threshold, the traditional paradigm of relying solely on process node scaling for performance enhancement has become increasingly untenable. In response to this technological impasse, semiconductor manufacturers have adopted a parallelization strategy, transitioning from single-core architectures to heterogeneous multi-core designs. This architectural evolution is exemplified by NVIDIA’s graphics processing unit (GPU) architectures (Markidis et al., 2018), which integrate thousands of streaming multiprocessors (SMs) as computational units, and Intel’s Core microarchitecture series (Hammarlund et al., 2014), which features sophisticated multi-core configurations with shared cache hierarchies. However, as die sizes approach the reticle limit of extreme ultraviolet (EUV) lithography systems, this scaling approach has led to significant challenges in defect density management. This, in turn, has resulted in diminished yield rates and escalating manufacturing costs (Han et al., 2024).