Ultrathin van der Waals ferroelectric oxides for scalable low-power memory

Abstract

With the continuous scaling of ferroelectric memories to below 5 nm, material and integration challenges that were previously manageable are now becoming increasingly prominent. At atomic thicknesses, conventional ferroelectric oxides suffer from depolarization fields, interfacial charge trapping and structural non-uniformity, leading to rapid performance degradation and poor device-to-device consistency. These issues have become a critical bottleneck for ferroelectric field-effect transistors (FeFETs), which are widely regarded as promising building blocks for low-power embedded non-volatile memory and computing-in-memory architectures. In the broader context of post-Moore electronics, where energy efficiency, three-dimensional integration and heterogeneous material platforms are increasingly demanded, the scalability of ferroelectric gate stacks has emerged as a central challenge. Although van der Waals ferroelectrics offer an appealing route to bypass dangling-bond-induced interface problems and critical-thickness limits, the lack of wafer-scale, CMOS-compatible ultrathin ferroelectric materials with robust polarization and high dielectric constants has so far limited their practical deployment. In a recent study published in Science (2026), Peng and colleagues report a wafer-scale, ultrathin van der Waals ferroelectric oxide platform that directly addresses several of these long-standing challenges. By leveraging a controlled oxidation strategy to transform a two-dimensional semiconductor precursor into a layered ferroelectric oxide, the authors establish a native-oxide route for constructing ferroelectric-semiconductor heterostructures with atomically smooth and chemically coherent interfaces. This materials-by-design approach departs from conventional top-down deposition of ferroelectric oxides onto semiconducting channels, a process that often introduces interfacial disorder, dangling-bond-related trap states and severe depolarization fields at nanometre thicknesses. Crucially, the resulting van der Waals ferroelectric oxide retains robust and switchable polarization down to the monolayer limit, as visualized by well-defined out-of-plane and in-plane domain writing and erasing processes. The coexistence of wafer-scale uniformity and atomic-scale ferroelectricity is particularly noteworthy: while two-dimensional ferroelectrics have previously been explored as model systems for studying polarization physics at the ultimate thickness limit, their limited lateral dimensions and poor integration compatibility have hindered device-level translation. In this work, the proposed platform helps close the long-standing gap between atomic-scale ferroelectric physics and practical, manufacturable device architectures.

1. Introduction

With the continuous scaling of ferroelectric memories to below 5 nm, material and integration challenges that were previously manageable are now becoming increasingly prominent. At atomic thicknesses, conventional ferroelectric oxides suffer from depolarization fields, interfacial charge trapping and structural non-uniformity, leading to rapid performance degradation and poor device-to-device consistency. These issues have become a critical bottleneck for ferroelectric field-effect transistors (FeFETs), which are widely regarded as promising building blocks for low-power embedded non-volatile memory and computing-in-memory architectures.

In the broader context of post-Moore electronics, where energy efficiency, three-dimensional integration and heterogeneous material platforms are increasingly demanded, the scalability of ferroelectric gate stacks has emerged as a central challenge. Although van der Waals ferroelectrics offer an appealing route to bypass dangling-bond-induced interface problems and critical-thickness limits, the lack of wafer-scale, CMOS-compatible ultrathin ferroelectric materials with robust polarization and high dielectric constants has so far limited their practical deployment.