Simulation and fabrication of vertical channel transistors with self-aligned high-κ metal gates using ion implantation for source/drain doping

• A novel source/drain ion implantation method for vertical channel transistors eliminates the need for dummy gates, simplifying fabrication and reducing costs. • TCAD simulations reveal that lightly doped regions (LDRs) naturally formed during implantation significantly influence device performance. • VCTs without dummy gates achieve approximately 27% higher on-state current (Ion) compared to those with dummy gates under identical implantation conditions. • Successful fabrication of both N-type and P-type VCTs validates the proposed implantation approach.