Key Takeaways & Executive Findings
- •• A novel source/drain ion implantation method for vertical channel transistors eliminates the need for dummy gates, simplifying fabrication and reducing costs. • TCAD simulations reveal that lightly doped regions (LDRs) naturally formed during implantation significantly influence device performance. • VCTs without dummy gates achieve approximately 27% higher on-state current (Ion) compared to those with dummy gates under identical implantation conditions. • Successful fabrication of both N-type and P-type VCTs validates the proposed implantation approach.
Abstract
In vertical channel transistors (VCTs), source/drain ion implantation (I/I) represents a significant technical challenge due to inherent three-dimensional structural constraints, which induce complications such as difficulties in dummy gate formation and shadowing effects of I/I. This article systematically investigates the impact of different implantation conditions on the performance of VCTs with and without dummy gates through TCAD simulation. It reveals the significant role of the lightly doped regions (LDRs) naturally formed due to ion implantation in source/drain of VCTs. Furthermore, it was found that VCT without dummy gates can achieve an approximately 27% increase in on-state current (Ion) under the same implantation conditions, and can greatly simplify the process flow and reduce costs. Finally, N-type and P-type VCTs were successfully fabricated using this implantation method.
1. Introduction
Vertical channel transistors (VCTs), characterized by their three-dimensional vertically stacked architecture of source, channel, and drain[1], overcome the physical limitations of contacted gate pitch (CGP)[2, 3], demonstrating superior electrical properties and significantly enhanced integration density[4−8]. However, its unique structure also poses considerable challenges to manufacturing, with source/drain ion implantation (I/I) doping being one of them[9]. In planar MOSFETs and FinFETs, source/drain implantation doping can be readily achieved through gate masking, naturally aligning with the gate. In comparison, the source, channel, and drain are no longer parallel to the substrate but arranged vertically in VCTs. This renders traditional methods ineffective, resulting in the decoupling of gate formation and source/drain doping, introducing two manufacturing challenges.
To address these issues, we previously reported a manufacturing method for VCTs that utilizes gate gaps to form self-aligned high-k metal gate (HKMG), filling dummy gates in the recesses to serve as shielding layers for the channel during source/drain I/I[10−12]. However, the formation of dummy gates is relatively complex, leading to increased process costs while simultaneously generating shadowing effects that substantially influence device performance[13, 14].
This paper proposes a novel source/drain I/I method for VCTs, which eliminates the need for dummy gates by utilizing the inherent structural features of the device to achieve source/drain doping wh
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Penghui Sun, Yongkui Zhang, Jun Luo (2025). Simulation and fabrication of vertical channel transistors with self-aligned high-κ metal gates using ion implantation for source/drain doping. SinoTechIntel Verified Research. https://doi.org/10.1088/1674-4926/25030043
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Frequently Asked Questions
What is the main challenge in source/drain doping for vertical channel transistors?
The main challenge is the three-dimensional structure, which makes traditional gate-masked implantation ineffective and introduces issues like dummy gate formation complexity and shadowing effects.
How does the proposed method simplify VCT fabrication?
The proposed method eliminates the need for dummy gates, simplifying the process flow and reducing costs while achieving comparable or better device performance.
What is the impact of removing dummy gates on device performance?
Removing dummy gates leads to approximately 27% increase in on-state current (Ion) under the same implantation conditions, as revealed by TCAD simulations.
What role do lightly doped regions (LDRs) play in VCTs?
LDRs naturally formed during ion implantation significantly influence device performance, and their presence is crucial for optimizing the electrical characteristics of VCTs.
Were both N-type and P-type VCTs successfully fabricated?
Yes, both N-type and P-type VCTs were successfully fabricated using the proposed implantation method, validating its practical applicability.
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