Key Takeaways & Executive Findings
- •• MgO tunnel barrier engineering reduces MTJ switching voltage while expanding write margin. • Achieved 85% array yield with sub-ppm bit error rates at low RA of 7 Ω·μm². • Process optimization enables low-power operation compatible with advanced CMOS nodes. • Enhanced write endurance and reliability for high-density STT-MRAM applications.
Abstract
Spin-transfer-torque magnetic random-access memory (STT-MRAM), based on magnetic tunnel junctions (MTJs), is attracting significant attention for applications demanding high reliability and speed. To ensure high TMR which is essential for achieving sufficient sense margin, MTJs typically incorporate relatively thick tunnel barriers, resulting in high operating voltages. As the CMOS technology nodes advance and operating voltages decrease, reducing the MTJ switching voltage becomes imperative. However, MTJs with thinner tunnel barriers generally exhibit significantly degraded read margins and bit error rate, presenting a major challenge for achieving high-density, low-power MRAM. Here, we address this challenge through MgO tunnel barrier engineering and process optimization, successfully reducing the required MOS driving voltage while simultaneously expanding the write margin. Meanwhile, 85% array yield with sub-parts-per-million bit error rates at RA = 7 Ω·μm2 is achieved. These advancements are promising for developing high-density MRAM at advanced technology nodes.
1. Introduction
Spin-transfer-torque magnetic random-access memory (STT-MRAM), leveraging magnetic tunnel junctions (MTJs), is a leading next-generation non-volatile memory technology that could replace embedded Flash and SRAM at technology nodes beyond 28 nm. Its applicability in industrial microcontrollers (MCUs), IoT systems, and data-centric artificial intelligence has been recently demonstrated. These advances predominantly rely on CoFeB (free layer)/MgO (tunnel barrier)/CoFeB (reference layer) MTJs.
Here, a key challenge arises from the MgO tunnel barrier. While sufficient thickness (~4 atomic layers) is essential to maintain high tunnel magnetoresistance (TMR)—critical for a robust read margin (on/off ratio)—it results in high MTJ switching voltage (Vc). In conventional one-transistor-one-MTJ (1T1MTJ) bit cells, this necessitates robust CMOS voltage delivery. However, as the technology nodes scale below 28 nm, CMOS operating voltages decrease (e.g., 0.8 V at 14 nm) and the gate oxide gets thinner. Generating the required MTJ drive voltage demands significant MOS transistor overdrive, severely degrading time-dependent dielectric breakdown (TDDB) lifetime and bit cell endurance. Moreover, integrating charge pump circuits to sustain operating voltage even higher than the value of I/O devices substantially increases peripheral circuit area and power consumption.
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Kunkun Li, Xiaolei Yang, Junlu Gong, Shikun He (2025). Realizing high-performance, enhanced write endurance of low-RA STT-MRAM through MgO tunnel barrier engineering. SinoTechIntel Verified Research. https://doi.org/10.1088/1674-4926/25080016
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Frequently Asked Questions
What is the main challenge addressed in this paper?
The main challenge is reducing the switching voltage of STT-MRAM while maintaining high TMR and read margin, as thinner tunnel barriers typically degrade performance. The authors address this through MgO tunnel barrier engineering and process optimization.
What are the key results achieved?
The authors achieved an 85% array yield with sub-parts-per-million bit error rates at a low RA of 7 Ω·μm², while reducing the required MOS driving voltage and expanding the write margin.
How does this work benefit advanced technology nodes?
By reducing the MTJ switching voltage, the approach enables compatibility with lower CMOS operating voltages at advanced nodes, improving endurance and reducing power consumption without sacrificing performance.
What is the significance of the RA value of 7 Ω·μm²?
A low RA (resistance-area product) is crucial for high-density MRAM as it allows for smaller cell sizes and faster operation. Achieving sub-ppm BER at this RA demonstrates the feasibility of high-performance, low-power STT-MRAM.
What is the role of MgO tunnel barrier engineering?
MgO tunnel barrier engineering involves optimizing the thickness and quality of the MgO layer to balance TMR and switching voltage. This allows for thinner barriers that reduce voltage while maintaining acceptable read margins and endurance.
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