• A lockstep-based pipeline hardening technique for a 32-bit MCU core reduces soft error rates in critical modules (PFU, DPU, Cache AXIM) from 40.07%, 26.36%, and 27.29% to 0%, 0.69%, and 1.11%, respectively.
• The proposed method achieves a 69.68% resource utilization compared to triple modular redundancy (TMR), significantly reducing FPGA area overhead.
• Recovery time is improved by 26.2% over software checkpoint roll-back, with average recovery cycles of 26,922.5 versus 36,479.06.
• The combined hardware-software approach effectively mitigates single-event upsets (SEUs) in microcontroller pipelines, enhancing fault tolerance for space applications.