Optimizing 55 nm split-gate memory for compute-in-memory: a focus on floating-gate engineering

• The 95-nm floating-gate length variant achieves a 5.35 V memory window, enabling robust multi-level storage. • A maximum conductance of 16.7 μS with excellent linearity is achieved under the varying voltage and width pulse scheme (VWPS). • The optimized device supports 32-state multi-level storage, enhancing compute-in-memory density and precision. • System-level evaluation demonstrates 92% training accuracy on CIFAR-10 with the VGG8 network, validating the device's potential for AI applications.