Key Takeaways & Executive Findings
- •• The 95-nm floating-gate length variant achieves a 5.35 V memory window, enabling robust multi-level storage. • A maximum conductance of 16.7 μS with excellent linearity is achieved under the varying voltage and width pulse scheme (VWPS). • The optimized device supports 32-state multi-level storage, enhancing compute-in-memory density and precision. • System-level evaluation demonstrates 92% training accuracy on CIFAR-10 with the VGG8 network, validating the device's potential for AI applications.
Abstract
The escalating need for high-performance artificial intelligence (AI) computing intensifies the "memory bottleneck" of the von Neumann architecture, prompting extensive exploration of computation-in-memory (CIM) solutions. This study is centered on the optimization of a high-efficiency, low-power "L"-shaped split-gate floating-gate (FG) memory for CIM applications. Fabricated on a 55 nm CMOS platform, the memory devices were systematically investigated through wafer acceptance test (WAT), Sentaurus™ simulations and comprehensive evaluations with the DNN + NeuroSim Framework V2.0. Among devices with diverse FG lengths, the 95-nm FG variant exhibits outstanding performance: it achieves a 5.35 V memory window, reaches a maximum conductance of 16.7 μS with excellent linearity under the varying voltage and width pulse scheme (VWPS), realizes 32-state multi-level storage, and attains a 92% training accuracy on the CIFAR-10 dataset using the VGG8 neural network.
1. Introduction
The burgeoning field of artificial intelligence and the escalating complexity of neural networks exacerbate the limitations of the traditional von Neumann architecture. The physical separation of processing and memory units in this architecture leads to substantial data transfer overhead, causing high power consumption (data transfer-related power can account for over 50% of total consumption) and significant latency (slowing down computing by more than 70%). Computing-in-memory (CIM) emerges as an innovative paradigm, integrating computational functions directly into memory to mitigate the memory bottleneck, reduce power usage, and enhance computational efficiency, thereby revolutionizing complex AI computations.
However, the development of suitable storage devices for CIM remains challenging. Various analog synaptic devices each have inherent limitations. Resistive random-access memory (RRAM) provides rapid read/write capabilities and high-density integration but faces challenges, including enlarged cell size due to anti-crosstalk design, elevated power usage, environmental sensitivity, and conductance nonlinearity that impairs neural network training accuracy. Phase-change memory (PCM) offers scalability and fast access but is challenge...
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Wanyi Ling, Ranran Liu, Kun Ren, Dianyu Qi, Yongyu Wu, Guangji Li, Miao Zhou, Qingshuang Xu, Zhenghui Xia, Xuan Li, Dertsyr Fan, Ichun Chuang, Tzung Wen Cheng, Chenming Tsai, Dawei Gao (2025). Optimizing 55 nm split-gate memory for compute-in-memory: a focus on floating-gate engineering. SinoTechIntel Verified Research. https://doi.org/10.1088/1674-4926/25060033
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Frequently Asked Questions
What is the main contribution of this paper?
The paper optimizes an L-shaped split-gate floating-gate memory on a 55 nm CMOS platform for compute-in-memory applications, demonstrating that a 95-nm floating-gate length achieves a 5.35 V memory window, 16.7 μS conductance, 32-state storage, and 92% training accuracy on CIFAR-10.
How does the 95-nm floating-gate variant perform compared to other lengths?
The 95-nm variant outperforms others by providing the largest memory window (5.35 V), highest conductance (16.7 μS) with excellent linearity, and supports 32-state multi-level storage, leading to superior system-level accuracy.
What evaluation methods were used in this study?
The devices were evaluated using wafer acceptance tests (WAT), Sentaurus™ simulations, and the DNN + NeuroSim Framework V2.0 for system-level performance assessment.
What is the significance of the 92% training accuracy on CIFAR-10?
The 92% accuracy on CIFAR-10 using the VGG8 network demonstrates that the optimized memory device can effectively support neural network training in compute-in-memory systems, achieving high performance while maintaining low power consumption.
What are the potential applications of this technology?
This technology is aimed at high-performance, low-power AI computing, particularly for edge devices and data-intensive applications where the memory bottleneck of von Neumann architectures is a critical issue.
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