• Optimized PR coating uniformity to 1.6% and applied four-zone ESC temperature control, reducing wafer-level uniformities of PR, SiN, and SiO2 to 6.3%, 2.3%, and 5.1%, respectively.
• Developed an over etch recipe with high selectivity (PR:SiN:SiO2 ≈ 1:1:6) to balance gate height loading between N- and PMOS regions.
• Precise EB1 time tuning enabled effective defect removal, and advanced KLA inspection ensured early detection of critical failure modes.
• The optimized PREB process provides a wider process window for subsequent AL CMP, establishing a robust and stable process for advanced logic device fabrication.