Key Takeaways & Executive Findings
- •• Optimized PR coating uniformity to 1.6% and applied four-zone ESC temperature control, reducing wafer-level uniformities of PR, SiN, and SiO2 to 6.3%, 2.3%, and 5.1%, respectively. • Developed an over etch recipe with high selectivity (PR:SiN:SiO2 ≈ 1:1:6) to balance gate height loading between N- and PMOS regions. • Precise EB1 time tuning enabled effective defect removal, and advanced KLA inspection ensured early detection of critical failure modes. • The optimized PREB process provides a wider process window for subsequent AL CMP, establishing a robust and stable process for advanced logic device fabrication.
Abstract
The introduction of high-k/metal gate (HK/MG) technology enables independent tuning of N-type metal−oxide−semiconductor (NMOS) and P-type metal−oxide−semiconductor (PMOS) threshold voltages, facilitating advanced nodes and improving overall chip performance. However, severe pattern loading effects during PMOS device fabrication pose challenges in dummy poly removal. This work reports the optimization of the photoresist etch back (PREB) process, providing a wider process window for subsequent AL CMP. By tuning the PR coating uniformity to 1.6% and applying four-zone electrostatic chuck (ESC) temperature control, the wafer-level uniformities of PR, SiN, and SiO2 were reduced to 6.3%, 2.3%, and 5.1%, respectively. An optimized over etch (OE) recipe with a high selectivity of PR : SiN : SiO2 ≈ 1 : 1 : 6 effectively balanced gate height loading between N- and PMOS regions. Furthermore, precise EB1 time tuning enabled defect removal, while advanced KLA inspection ensured early detection of critical failure modes. Collectively, these measures establish a robust and stable PREB process for advanced logic device fabrication.
1. Introduction
As the final generation of planar Complementary metal−oxide−semiconductor (CMOS) technology, HK process strikes a compelling balance between performance and cost, offering vast potential across high-end applications such as the internet of things (IoT), artificial intelligence (AI), automotive electronics, and 5G communications. SiGe technology, a cornerstone for enhancing PMOS device performance, simultaneously amplifies structural differences among Input/Output (IO) large MOS, NMOS, and PMOS devices—differences that significantly impact the subsequent dummy poly removal process.
Specifically, during the PMOS source−drain (PSD) plasma dry etching step, partial erosion of the SiO2 hard mask over the PMOS region results in significantly thicker hard masks over large poly structures and core NMOS regions compared to core PMOS regions. Consequently, this leads to insufficient removal during subsequent interlayer dielectric zero chemical mechanical planarization (ILD0 CMP), making complete elimination of PMOS dummy poly challenging, which subsequently affects metal gate filling. These issues typically have critical impacts, causing severe deviations in the final product yield. The PREB process has been developed to alleviate these challenges. By employing the photoresist (PR) as a temp
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Ting Lei, Zhehong Liu, Zhiwen Liu, Guangjie Xue, Chun Sun, Jun Zhou, Xiangshui Miao (2025). Optimization and defect control in photoresist etch back processes for advanced semiconductor technologies. SinoTechIntel Verified Research. https://doi.org/10.1088/1674-4926/25070024
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Frequently Asked Questions
What is the PREB process in semiconductor manufacturing?
PREB (Photoresist Etch Back) is a process used in semiconductor manufacturing to remove dummy poly structures by using photoresist as a temporary mask and etching back layers to achieve uniform gate heights, particularly in high-k/metal gate technologies.
Why is pattern loading effect a challenge in PMOS device fabrication?
Pattern loading effect causes non-uniform etching rates across different pattern densities, leading to thicker hard masks over large poly structures and core NMOS regions compared to core PMOS regions. This results in insufficient removal of PMOS dummy poly during ILD0 CMP, affecting metal gate filling and yield.
How does the optimized PREB process improve wafer uniformity?
By tuning PR coating uniformity to 1.6% and applying four-zone electrostatic chuck (ESC) temperature control, the wafer-level uniformities of PR, SiN, and SiO2 were reduced to 6.3%, 2.3%, and 5.1%, respectively, leading to better process control.
What is the significance of the over etch recipe selectivity in PREB?
An optimized over etch recipe with high selectivity (PR:SiN:SiO2 ≈ 1:1:6) effectively balances gate height loading between N- and PMOS regions, ensuring uniform removal and preventing defects.
How does defect control contribute to the PREB process?
Precise EB1 time tuning enables effective defect removal, and advanced KLA inspection ensures early detection of critical failure modes, thereby enhancing the robustness and stability of the PREB process.
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