• Conventional PLL-based divider chains and multi-core LC oscillators face scalability challenges as operating frequencies approach transistor cutoff frequency (fT), including limited speed, power efficiency, and phase-count scalability.
• LC-based designs incur substantial area overhead, limited phase counts, and increased sensitivity to device mismatch, degrading phase accuracy as the number of phases increases.
• Passive phase-shifting networks, such as coupled-resonator-based quadrature hybrids (CRQHs), offer alternative approaches for multi-phase clock generation, potentially overcoming some limitations of active techniques.
• Future multi-phase clock generation techniques must address the stringent requirements of high-speed wireline and wireless systems, including RMS jitter, phase accuracy, and robustness against PVT variations.