• Proposes GC bypass, a novel architecture that decouples garbage collection from the flash translation layer to reduce long-tail latency in SSDs.
• Utilizes dedicated controllers and priority-aware scheduling to ensure user I/O preempts low-priority GC operations, mitigating path conflicts.
• Achieves up to 25% reduction in the 99.99th percentile long-tail latency compared to the state-of-the-art Venice scheme.
• Maintains the benefits of path diversity while effectively isolating critical I/O from background maintenance tasks.