GC bypass: decoupling GC from the flash translation layer to eliminate GC-induced long-tail latency inside SSD

Abstract

NAND flash-based solid-state drives (SSDs) have been adopted by many data centers due to their high performance and low power consumption. However, the physical characteristics of the underlying flash memory necessitate garbage collection (GC) operations. Valid page migration during GC contributes significantly to latency overhead while competing for flash channel bandwidth and controller resources with user I/O requests through shared physical paths, leading to path conflicts and elevated long-tail latency. The existing Venice scheme introduces a low-cost interconnected network with path reservation mechanisms to provide substantial path diversity for SSDs. Nevertheless, its fair scheduling policy lacks priority differentiation between I/O and GC requests. In this paper, we propose GC bypass, which leverages Venice’s path diversity while enforcing GC request transmission through dedicated controllers. GC bypass decomposes GC requests into sub-requests and assigns low priority to valid page writes, enabling high-priority operations including user I/O, valid page reads, and block erases, to preempt paths reserved by low-priority requests. Valid pages failing to secure reserved paths are temporarily buffered for retry. Experimental results demonstrate that GC bypass reduces the 99.99th percentile long-tail latency by up to 25% compared to Venice. GC bypass effectively mitigates interference between critical I/O operations and background maintenance tasks while maintaining the architectural benefits of path diversity.

1. Introduction

With data-intensive workloads, such as artificial intelligence and high-performance computing, increasingly dominating data centers, NAND flash-based solid-state drives (SSDs) have widely replaced traditional hard disk drives (HDDs) as the primary storage components in data centers. SSDs exhibit significant advantages in multiple aspects due to their superior bandwidth, performance, reliability, and energy efficiency. In data center environments, SSDs face numerous challenges, one of the most critical being the long-tail latency caused by garbage collection (GC). GC not only occupies storage cells within flash chips but also directly competes with user I/O requests on the physical channel bus, leading to temporary suspension of I/O requests and creating a significant performance bottleneck. Although SSDs are designed with multiple independent physical channels connecting flash chips, theoretically enabling parallel processing of multiple requests, when valid page migration operations and user I/O access the same channel or chip simultaneously, SSDs are forced to serialize concurrent requests to serial execution, a phenomenon known as “path conflict.” Path conflicts undermine the parallel advantages of SSD multi-channel architectures and lead to two key performance issues. When GC operations preempt channel resources, interrupted user I/O may experience millisecond-level waiting delays. In sustained write scenarios or when SSDs approach full capacity, frequently triggered GC prolongs the queuing time of I/O requests, resulting in long-tail latency. Additionally, since GC typically employs a threshold-triggered mechanism, its execution causes intermittent I/O performance fluctuations.

To mitigate the long-tail latency caused by GC, researchers focus on optimizing GC firmware algorithms and improving scheduling schemes between GC and I/O. However, firmware-based GC optimization still has limitations: it can operate only within the constraints of the existing hardware architecture and cannot fundamentally alter the allocation and utilization of hardware resources. Moreover, the effectiveness of firmware optimization largely depends on the specific implementation and the quality of the optimization algorithms, which may vary across different SSD manufacturers and models, thereby increasing the difficulty and uncertainty of optimization. Existing studies have proposed various optimization techniques at the logical scheduling level, such as dynamically adjusting the priority weights of GC and user I/O (Lee et al., 2013; Yan et al., 2017; Mao et al., 2018), performing fine-grained GC operations during I/O request intervals (Kang et al., 2017; Paik et al., 2018; Sha et al., 2021), or exploiting intra-flash parallelism by parallelizing GC tasks (Gao et al., 2017, 2020b). While these schemes can partially alleviate resource contention under traditional multi-channel shared bus architectures, they still face inherent limitations due to the lack of dedicated path support.