Key Takeaways & Executive Findings
- •• FTHOE is a virtual-channel-less fault-tolerant routing algorithm for wafer-scale interconnection networks, combining Hamiltonian routing with the odd-even turn model to achieve load balancing. • The algorithm dynamically adjusts output port selection priority using local fault vector information, shortening detour paths and reducing the probability of packet trapping in faulty regions. • FTHOE preserves minimal path diversity and adaptivity under fault conditions, enhancing network load-balancing and communication performance. • Simulations show that FTHOE significantly reduces average network latency and improves throughput compared to existing fault-tolerant routing algorithms in complex fault scenarios.
Abstract
As application scenarios continue to grow in complexity, wafer-scale systems impose increasingly stringent requirements on the reliability of interconnection networks. Under inevitable process-induced manufacturing defects and environmental disturbances, node and link faults occur frequently in wafer-scale interconnection networks, making fault tolerance a key factor in improving overall system reliability. To address chiplet node faults and link faults in wafer-scale interconnection networks, this paper proposes a load-balancing virtual-channel-less fault-tolerant routing algorithm, termed FTHOE. The proposed algorithm is based on a Hamiltonian routing strategy and the odd–even turn model. By exploiting local fault vector information at the current node, FTHOE dynamically adjusts the output port selection priority, thereby shortening detour paths around faulty regions while effectively reducing the probability of packets being trapped in fault neighborhoods. At the same time, FTHOE preserves a relatively high degree of minimal path diversity by retaining the adaptiveness of Hamiltonian-based routing under fault conditions, thereby enhancing network load-balancing and overall communication performance. Simulation results demonstrate that, compared with existing fault-tolerant routing algorithms, FTHOE significantly reduces average network latency and improves throughput, exhibiting robust fault tolerance and load-balancing performance under complex fault scenarios.
1. Introduction
With the gradual slowdown of Moore's law (Moore, 1998) and the breakdown of Dennard scaling (Bohr, 2007), the traditional approach of achieving performance improvements solely through transistor scaling has become increasingly unsustainable. Conventional integrated circuit design is therefore confronted with multiple constraints simultaneously, including physical, packaging, and yield limits. Against this background, wafer-scale systems, which integrate a large number of pre-fabricated chiplets for computation, memory, and specialized acceleration on a single wafer, have gradually emerged as an important development direction for high-performance computing in the post-Moore era. Compared with single-chip solutions that rely on advanced process nodes, wafer-scale systems can achieve higher bandwidth density, lower communication latency, and better energy efficiency using more mature process technologies (Hu et al., 2024).
In recent years, both industry and academia have made significant progress in wafer-scale integration and emerging system architectures. For example, the wafer-scale engine (WSE) series (Pal et al., 2021) developed by Cerebras Systems integrates hundreds of thousands of computing cores on a single wafer and enables ultra-large-scale parallel computation through a high-bandwidth interconnection network. Tesla's Dojo system (Pal et al., 2019) constructs wafer-scale interconnects using a regular two-dimensional (2D) topology, achieving efficient inter-chiplet communication. In addition, a software-defined system on wafer (SDSoW) (Wu et al., 2024) reconstructs the system design paradigm through hardware–software co-design, providing a new technological path for large-scale heterogeneous integration. These representative systems collectively indicate that the interconnection network has become a key infrastructure determining the performance, energy efficiency, and reliability of wafer-scale systems.
Loading authentic research manuscript (Pages 1–5)...
Shuaikang Hou, Qinrang Liu, Wenbo Zhang, Ping Lv, Peijie Li, Wei Guo (2025). FTHOE: a Hamiltonian-driven fault-tolerant routing algorithm for wafer-scale interconnection networks. Engineering Information Technology & Electronic Engineering. https://doi.org/10.1631/ENG_ITEE_2025_0005
Research & Educational Purpose Only:The translations, structured abstracts, analytical annotations, and data reports provided by SinoTechIntel are intended exclusively for academic research, internal corporate R&D, and educational benchmarking. They do not constitute formal engineering, chemical safety, legal, or professional advice.
Copyright & Intellectual Property Notice: Original copyright of the underlying source articles and experimental data remains with the respective authors, institutions, and original publishing journals. SinoTechIntel claims intellectual property only over its proprietary translations, analytical syntheses, and AEO structured enhancements in accordance with international fair use and academic citation principles.
Frequently Asked Questions
What is FTHOE?
FTHOE is a Hamiltonian-driven fault-tolerant routing algorithm proposed for wafer-scale interconnection networks. It uses local fault vector information and the odd-even turn model to dynamically adjust output port selection priority, thereby shortening detour paths around faulty regions and reducing the probability of packets being trapped in fault neighborhoods.
What types of faults does FTHOE address?
FTHOE addresses both chiplet node faults and link faults in wafer-scale interconnection networks. These faults can arise from process-induced manufacturing defects and environmental disturbances.
How does FTHOE improve network performance?
FTHOE improves network performance by reducing average network latency and increasing throughput under complex fault scenarios. It maintains a high degree of minimal path diversity and adaptivity, enhancing load balancing and overall communication performance.
What is the significance of wafer-scale systems?
Wafer-scale systems integrate a large number of pre-fabricated chiplets on a single wafer, enabling higher bandwidth density, lower communication latency, and better energy efficiency in the post-Moore era. They are considered a key direction for high-performance computing.
What are the key design mechanisms of FTHOE?
FTHOE combines a Hamiltonian routing strategy with the odd-even turn model. It exploits local fault vector information at each node to dynamically adjust output port selection priority, shortening detour paths and preventing packet trapping while preserving adaptiveness and load balancing.
Related Technical Papers & Translations
Design and optimization of a high-efficiency distillation process for cellulosic fuel ethanol integrated with thermal coupling and molecular sieve adsorption
To address the challenges of high energy consumption and prominent costs in the traditional three-columns distillation process for cellulosic fuel ethanol, a distillation—molecular sieve coupling separation process is proposed. This process integrates a three-column (crude distillation column, first distillation column, second distillation column) system with a 3A molecular sieve adsorption deep dehydration unit. A thermal coupling network is constructed via differential pressure design (steam from medium/high-pressure columns as mutual heat sources, reboiler liquid waste heat for feed preheating), and molecular sieve adsorption conditions are optimized. The study first performs a thermodynamic consistency test on the ethanol—water system, determines optimal non-random two-liquid (NRTL) model binary interaction parameters via experimental data regression for Aspen Plus simulation. Aiming at minimum total annual cost (TAC), Aspen Plus is used to optimize process parameters (theoretical tray number, feed location, reflux ratio, side-draw position, etc.). Economic analysis shows this process reduces CO2 emission costs by 27.56%, TAC by 15.58% (to 5.123 × 106 USD·a-1), and increases ethanol purity to ＞99.6%, providing an effective solution for green, efficient separation.
A cohesion loss model for determining residual strength of deep bedded sandstone
Rock residual strength, as an important input parameter, plays an indispensable role in proposing the reasonable and scientific scheme about stope design, underground tunnel excavation and stability evaluation of deep chambers. Therefore, previous residual strength models of rocks established were reviewed. And corresponding related problems were stated. Subsequently, starting from the effects of bedding and whole life-cycle evolution process, series of triaxial mechanical tests of deep bedded s
Federated model with contrastive learning and adaptive control variates for human activity recognition
Recent attention to privacy issues demands a communication-safe method for training human activity recognition (HAR) models on client activity data. Federated learning (FL) has become a compelling technique to facilitate model training between the server and clients while preserving data privacy. However, classical FL methods often assume independent and identically distributed (IID) data among clients. This assumption does not hold true in practical scenarios. Human activity in real-world scena