From software-defined interconnect to software-defined system-on-wafer: a computing architecture revolution in the post-Moore era

Abstract

As Moore’s law approaches its fundamental physical and economic limits, the semiconductor industry faces unprecedented challenges in maintaining performance growth. This study presents the revolutionary evolution from software-defined interconnect (SDI) to software-defined system-on-wafer (SDSoW), a paradigm-shifting architectural approach that transcends traditional scaling constraints through wafer-level heterogeneous integration. Our proposed SDSoW enables dynamic reconfiguration of thousands of computing chiplets across an entire wafer, achieving superlinear performance scaling and significantly improving energy efficiency. We establish a comprehensive theoretical framework with mathematical models covering key aspects, such as interconnect flexibility and integration scaling, and propose an application-driven dynamic architecture reconfiguration (ADR) paradigm that optimizes wafer-scale resources in real time and may foster emergent intelligence in large, heterogeneous systems. Simulation results (128–1024 nodes) demonstrate that SDSoW outperforms conventional multi-chip systems, delivering approximately 3.73×–4.39× higher throughput, 79.2% lower latency, and 2.8× higher power efficiency. As a paradigm shift comparable to the invention of integrated circuits (ICs), it provides a viable pathway beyond Moore’s law through innovative architectural design rather than process scaling.

1. Introduction

Moore’s law, the foundational principle that has driven semiconductor progress for over five decades, now faces fundamental physical and economic limits (Khan et al., 2018; Leiserson et al., 2020). The exponential increase in transistor density, as predicted by Gordon Moore in 1965, has enabled unprecedented computational advances but is increasingly being challenged by quantum tunneling effects, manufacturing complexity, and escalating costs (Theis and Wong, 2017; Shalf, 2020).

Traditional scaling approaches face critical limitations at advanced process nodes below 7 nm, where leakage currents, variability, and thermal effects severely impact performance and reliability (Radamson et al., 2020). The economic burden of next-generation fabrication facilities, exceeding $20 billion per facility, has made continued scaling economically unsustainable for most applications (Khan et al., 2018; Shalf, 2020).

The evolution of semiconductor integration paradigms shows a clear trajectory from system-on-chip (SoC) through two and one-half dimensional (2.5D)/three-dimensional (3D) chiplet architectures toward wafer-level integration (Lau, 2022). Each paradigm shift has enabled new levels of performance and functionality while addressing the limitations of previous approaches.

This study introduces software-defined system-on-wafer (SDSoW), a revolutionary architectural approach that fundamentally redefines computing system design. SDSoW leverages wafer-level integration with software-defined interconnect (SDI) to create massively parallel, dynamically reconfigurable systems that achieve performance scaling beyond Moore’s law constraints.