• An innovative detection method for the depletion layer in the JFET region of SiC MOSFETs is proposed for the first time.
• The influence of JFET width on the gate voltage (Vg) and gate oxide capacitance (Cg) is systematically analyzed for hexagonal and linear cell topologies.
• The robustness of different cell topologies and JFET widths is evaluated through high temperature gate reverse bias (HTGB−) reliability tests.
• The study provides insights into optimizing cell topology and JFET width to enhance device reliability by reducing gate oxide electric field.