Key Takeaways & Executive Findings
- •• An innovative detection method for the depletion layer in the JFET region of SiC MOSFETs is proposed for the first time. • The influence of JFET width on the gate voltage (Vg) and gate oxide capacitance (Cg) is systematically analyzed for hexagonal and linear cell topologies. • The robustness of different cell topologies and JFET widths is evaluated through high temperature gate reverse bias (HTGB−) reliability tests. • The study provides insights into optimizing cell topology and JFET width to enhance device reliability by reducing gate oxide electric field.
Abstract
High gate oxide electric field, which can lead to device failure, is a common issue in SiC MOSFETs. To mitigate this issue and ensure high device reliability, an electric field shielding layer (also called depletion layer) in JFET region is always used to reduce the gate oxide electric filed strength (Eox,max). However, there is still a lack of a detection methods to characterize the changes in the depletion layer of the JFET region. In this paper, a type of 1200 V 4H-SiC MOSFET with different JFET widths and cell topologies is designed and fabricated, and an innovative detection method for the depletion layer of JFET region is proposed for the first time. This method is adopted to focus on discussing the influence of the depletion layer formed by different JFET widths on Vg, and the changes in the gate oxide capacitance Cg of hexagonal cells and linear cells during the formation of the JFET depletion layer are studied. Finally, the robustness of different cell topologies and JFET widths is determined by the depletion voltage drift in the high temperature gate reverse bias tests (HTGB−) reliability test.
1. Introduction
In recent years, with the wide application of power electronic systems in photovoltaic, new energy vehicles, smart grid and other fields, the market demand for high temperature, high frequency, and high voltage devices has been increasing[1−4]. Compared with traditional silicon-based power devices, silicon carbide (SiC) power devices have the characteristics of wider band gap, high saturated electron drift speed, high breakdown field strength, and high thermal conductivity, etc.[5−8]. These characteristics determine the advantages of SiC MOSFET with low on-resistance, high power density and high temperature resistance, and become one of the most promising devices[9, 10].
However, during the manufacturing process of SiC MOSFET devices, due to process fluctuations and the 4H-SiC materials itself, the electric parameters of the devices will fluctuate to varying degrees. And some interface states will also occur more or less at the gate oxide interface, resulting in reduced robustness and poorer reliability in the mass-produced 4H-SiC MOSFET[11−13]. Especially, when the SiC MOSFET is turned off at Vgs = −5 V for a period of time, the existence of the interface charge at the gate oxide will change the potential boundary conditions on the semiconductor surface, thereby affecting the formation of the entire depletion layer. As one of the core regions of the PN junction, the depletion layer can effectively modulate the electric field distribution within the device, suppress the peak electric field at critical positions.
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Bofeng Zheng, Houcai Luo, Huan Wu, Jingping Zhang, Xianping Chen (2025). Effects of cell topology and JFET width on depletion layer of SiC MOSFET. SinoTechIntel Verified Research. https://doi.org/10.1088/1674-4926/25060030
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Frequently Asked Questions
What is the main challenge addressed in this paper?
The main challenge is the high gate oxide electric field in SiC MOSFETs, which can lead to device failure. The paper proposes a detection method for the depletion layer in the JFET region to mitigate this issue.
What is the innovative method proposed in this study?
The paper proposes an innovative detection method for the depletion layer in the JFET region of SiC MOSFETs, which is used to study the influence of JFET width and cell topology on gate voltage and gate oxide capacitance.
How does JFET width affect the device performance?
The study shows that different JFET widths influence the formation of the depletion layer, which in turn affects the gate voltage (Vg) and gate oxide capacitance (Cg). This impacts the electric field distribution and device reliability.
What are the key findings regarding cell topologies?
The paper compares hexagonal and linear cell topologies, analyzing changes in gate oxide capacitance during depletion layer formation. The robustness of these topologies is evaluated through HTGB− reliability tests.
What is the significance of the HTGB− reliability test in this study?
The HTGB− (high temperature gate reverse bias) test is used to determine the robustness of different cell topologies and JFET widths by measuring depletion voltage drift, providing insights into long-term reliability.
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