• Proposes a novel cluster-based BIST architecture for M3D ICs that efficiently detects and localizes inter-layer via (ILV) faults.
• Groups ILVs by fault probability and uses a walking pattern approach, enabling detection of all stuck-at and bridging faults plus most multiple faults.
• Reduces test configurations and test time compared to existing methods while improving area and hardware efficiency, especially for large benchmarks.
• In LU32PEENG benchmark with 64 ILV clusters, power/area/hardware overheads minimized to 0.82%, 1.03%, and 1.14%.