Key Takeaways & Executive Findings
- •• Proposes a novel cluster-based BIST architecture for M3D ICs that efficiently detects and localizes inter-layer via (ILV) faults. • Groups ILVs by fault probability and uses a walking pattern approach, enabling detection of all stuck-at and bridging faults plus most multiple faults. • Reduces test configurations and test time compared to existing methods while improving area and hardware efficiency, especially for large benchmarks. • In LU32PEENG benchmark with 64 ILV clusters, power/area/hardware overheads minimized to 0.82%, 1.03%, and 1.14%.
Abstract
Monolithic three-dimensional integrated circuits (M3D ICs) have emerged as an innovative solution to overcome the limitations of traditional 2D scaling, offering improved performance, reduced power consumption, and enhanced functionality. Inter-layer vias (ILVs), crucial components of M3D ICs, provide vertical connectivity between layers but are susceptible to manufacturing and operational defects, such as stuck-at faults (SAFs), shorts, and opens, which can compromise system reliability. These challenges necessitate advanced built-in self-test (BIST) methodologies to ensure robust fault detection and localization while minimizing the testing overhead. In this paper, we introduce a novel BIST architecture tailored to efficiently detect ILV defects, particularly in irregularly positioned ILVs, and approximately localize them within clusters, using a walking pattern approach. In the proposed BIST framework, ILVs are grouped according to the probability of fault occurrence, enabling efficient detection of all SAFs and bridging faults (BFs) and most multiple faults within each cluster. This strategy empowers designers to fine-tune fault coverage, localization precision, and test duration to meet specific design requirements. The new BIST method addresses a critical shortcoming of existing solutions by significantly reducing the number of test configurations and overall test time using multiple ILV clusters. The method also enhances efficiency in terms of area and hardware utilization, particularly for larger circuit benchmarks. For instance, in the LU32PEENG benchmark, where ILVs are divided into 64 clusters, the power, area, and hardware overheads are minimized to 0.82%, 1.03%, and 1.14%, respectively.
1. Introduction
The demand for high-performance computing (HPC) is rapidly increasing due to technological advancements (Garcia-Buendia et al., 2024). Extensive computing power is essential for efficiently processing and analyzing large datasets. Consequently, there is a growing need for high-performance processors to support the large-scale computational requirements of high-demand applications ranging from artificial intelligence (AI)-based systems and edge computing to Internet of Things (IoT) devices (Zhou et al., 2024). However, due to physical limitations, transistor shrinking is reaching its limit, leading to the end of Moore’s law. Monolithic three-dimensional integrated circuits (M3D ICs) have emerged as an innovative solution to overcome the limitations of traditional two-dimensional (2D) scaling, offering improved performance, reduced power consumption, and enhanced functionality (Kim S and Park, 2024). High bandwidth memory (HBM) is a prime example and one of the first technologies to use this approach to improve performance (Huang et al., 2025).
One of the key features of M3D ICs is the use of vertical vias, known as inter-layer vias (ILVs). These vias are essential for establishing vertical connections between different layers, facilitating the integration of heterogeneous technologies, and enabling efficient routing of signals and power. However, while ILVs offer significant advantages, they can also pose a critical vulnerability, potentially affecting system reliability. The fabrication of ILVs presents several challenges, particularly regarding defects that may arise during manufacturing or operation. Issues such as missing or misaligned vias, poor metal fill, and the formation of voids can degrade signal integrity and compromise overall system performance. Therefore, the detection of these defects is crucial to maintaining the functionality and reliability of M3D ICs (Chen et al., 2024).
Traditional testing methods often fall short in detecting ILV defects due to their vertical orientation and high aspect ratio, necessitating the development of new, non-destructive, and efficient testing methods. To meet these demands, the built-in self-test (BIST) has emerged as a promising solution. BIST offers an efficient, low-cost, and non-destructive approach to IC testing, making it particularly suitable for ILVs in M3D ICs. By providing targeted and efficient testing of vertical connections, BIST reduces the time and costs associated with traditional testing methods while ensuring the quality and reliability of M3D ICs. As M3D IC technology continues to evolve, advancing ILV testing methodologies remains a critical area of research and development (Pentapati and Lim, 2024).
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Hadi JAHANIRAD, Ahmad MENBARI, Hemin RAHIMI, Daniel ZIENER (2025). Effective fault detection in M3D ICs: a cluster-based BIST for enhanced inter-layer via fault coverage. Frontiers of Information Technology & Electronic Engineering. https://doi.org/10.1631/FITEE_2401094
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Frequently Asked Questions
What is the main contribution of this paper?
The paper introduces a novel cluster-based BIST architecture for M3D ICs that efficiently detects and localizes inter-layer via (ILV) faults, particularly those in irregularly positioned ILVs, using a walking pattern approach.
What types of faults are targeted by the proposed BIST method?
The proposed BIST method targets stuck-at faults (SAFs), bridging faults (BFs), and most multiple faults within clusters of inter-layer vias.
How does the proposed BIST reduce testing overhead compared to existing solutions?
By grouping ILVs into multiple clusters based on fault probability, the method significantly reduces the number of test configurations and overall test time, while also improving area and hardware utilization.
What are the quantitative results for the LU32PEENG benchmark?
For the LU32PEENG benchmark with 64 ILV clusters, the power overhead is minimized to 0.82%, area overhead to 1.03%, and hardware overhead to 1.14%.
Why is BIST particularly suitable for testing ILVs in M3D ICs?
BIST offers a non-destructive, low-cost, and efficient testing approach that addresses the vertical orientation and high aspect ratio challenges of ILVs, reducing time and costs compared to traditional testing methods.
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