Contact planarization and passivation lift tungsten diselenide PMOS performance

• Innovative surface preparation and passivation techniques reduce process residues and improve device uniformity, leading to a two-order-of-magnitude increase in drain current. • Contact engineering and gate oxide scaling are critical for reducing contact resistance and threshold voltage, achieving subthreshold swings as low as 200 mV/dec. • The studies demonstrate record performance in WSe2 p-channel transistors, making them more competitive for scaled CMOS logic applications. • The findings provide a roadmap for overcoming Fermi-level pinning and interface quality issues in 2D TMDs, advancing the potential of WSe2 in extending Moore's Law.