Key Takeaways & Executive Findings
- •• Innovative surface preparation and passivation techniques reduce process residues and improve device uniformity, leading to a two-order-of-magnitude increase in drain current. • Contact engineering and gate oxide scaling are critical for reducing contact resistance and threshold voltage, achieving subthreshold swings as low as 200 mV/dec. • The studies demonstrate record performance in WSe2 p-channel transistors, making them more competitive for scaled CMOS logic applications. • The findings provide a roadmap for overcoming Fermi-level pinning and interface quality issues in 2D TMDs, advancing the potential of WSe2 in extending Moore's Law.
Abstract
Two-dimensional (2D) transition metal dichalcogenides (TMDs) have superior electrical and optical properties that challenge the limits of traditional bulk semiconductors. Tungsten diselenide (WSe2) is a promising p-type channel material for advanced CMOS logic technology, but its performance has been limited by high contact resistance, poor interface quality, and unstable device behavior. This NEWS AND VIEWS article highlights two groundbreaking studies presented at the 2025 VLSI Symposium that demonstrate record performance in WSe2 p-channel transistors through innovative engineering, including surface conditioning, contact engineering, gate oxide scaling, and passivation. The studies achieve significant improvements in monolayer and multilayer WSe2 transistors, addressing key challenges and paving the way for scalable p-type transistors.
1. Introduction
Two-dimensional (2D) transition metal dichalcogenides (TMDs), which allow atomic-scale manipulation, have superior electrical and optical properties that challenge the limits of traditional bulk semiconductors like silicon. As a representative TMD and a promising 2D channel material for high-performance, scalable p-type transistors, tungsten diselenide (WSe2) has attracted considerable academic and industrial interest for its potential in advanced complementary metal−oxide−semiconductor (CMOS) logic technology and in extending Moore’s Law.
After years of research and development, the basic properties of WSe2 are now well understood. However, compared to n-type TMDs such as molybdenum disulfide (MoS2)—where researchers have achieved low-resistance contacts and high carrier mobilities—WSe2 still lags behind. WSe2 device performance has been limited by strong Fermi-level pinning at the contacts, poor interface quality, and unstable device behavior. These factors lead to high contact resistance (Rc), resulting in high threshold voltages (Vth), suboptimal subthreshold swings (SS), and significant hysteresis.
Recently, two groundbreaking studies presented at the 2025 VLSI Symposium unveiled pathways to overcome these hurdles, demonstrating record performance in WSe2 p-channel transistors through innovative engineering. Each study tackles the problem from different angles—including surface conditioning, contact engineering, gate oxide scaling, and passivation—and each achieves significant performance improvements in monolayer and multilayer WSe2 transistors. In this "NEWS AND VIEWS" article, we briefly highlight their key ideas and results.
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Haoyu Peng, Ping-Heng Tan, Jiangbin Wu (2025). Contact planarization and passivation lift tungsten diselenide PMOS performance. SinoTechIntel Verified Research. https://doi.org/10.1088/1674-4926/25080028
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Frequently Asked Questions
What is the main challenge for WSe2 p-type transistors?
The main challenges include high contact resistance due to Fermi-level pinning, poor interface quality, and unstable device behavior, leading to high threshold voltages and suboptimal subthreshold swings.
How did the studies improve WSe2 transistor performance?
The studies employed innovative engineering approaches such as surface conditioning, contact planarization, passivation, and gate oxide scaling, which reduced process residues, improved device uniformity, and significantly enhanced drain current and subthreshold swing.
What were the key results from the TSMC study?
The TSMC study achieved a two-order-of-magnitude increase in drain current, threshold voltage around -1.4 to -1.3 V, and subthreshold swing reduced to 200 mV/dec by improving surface preparation and passivation.
Why is WSe2 important for future electronics?
WSe2 is a promising 2D channel material for p-type transistors, essential for complementary metal-oxide-semiconductor (CMOS) logic technology, and could help extend Moore's Law by enabling further miniaturization and performance improvements.
What is the significance of the 2025 VLSI Symposium studies?
These studies demonstrate record performance in WSe2 p-channel transistors, providing a roadmap to overcome long-standing limitations and making WSe2 more competitive for scaled CMOS applications.
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