• A novel LDMOS with split gate and split contact field plate (CFP) is proposed, requiring no extra bias, masks, or process steps, ensuring full BCD compatibility.
• TCAD simulations reveal that the split gate reduces specific on-resistance (Ron,sp) by forming an accumulation layer, while the split CFP and gate introduce additional electric-field peaks to maintain high breakdown voltage (BV).
• Compared to conventional CFP-LDMOS, the proposed device achieves an 8.52% reduction in Ron,sp without compromising BV, leading to an 8.07% improvement in figure of merit (FOM).
• The proposed structure is scalable to various voltage levels in BCD platforms, demonstrating broad applicability in power management and automotive electronics.