Key Takeaways & Executive Findings
- •• A novel LDMOS with split gate and split contact field plate (CFP) is proposed, requiring no extra bias, masks, or process steps, ensuring full BCD compatibility. • TCAD simulations reveal that the split gate reduces specific on-resistance (Ron,sp) by forming an accumulation layer, while the split CFP and gate introduce additional electric-field peaks to maintain high breakdown voltage (BV). • Compared to conventional CFP-LDMOS, the proposed device achieves an 8.52% reduction in Ron,sp without compromising BV, leading to an 8.07% improvement in figure of merit (FOM). • The proposed structure is scalable to various voltage levels in BCD platforms, demonstrating broad applicability in power management and automotive electronics.
Abstract
To improve the breakdown voltage (BV)−specific on-resistance (Ron,sp) trade-off and enhance manufacturability, this article proposes a novel lateral diffused metal−oxide−semiconductor (LDMOS) structure that features a split gate and split contact field plate (CFP). This novel structure requires no additional bias voltages, masks, or process steps, making it fully compatible with the bipolar-CMOS-DMOS (BCD) process flow. The physical mechanisms are elucidated through technology computer-aided design (TCAD) simulations. In the on-state, the positively biased split gate forms an accumulation layer at the drift region surface, thereby reducing Ron,sp. In the off-state, both the split gate and split CFP introduce additional electric-field peaks that smooth the lateral electric field, thus preserving a high BV. Compared with the conventional CFP-LDMOS, the proposed CFP-LDMOS achieves an 8.52% reduction in Ron,sp without compromising BV, leading to an 8.07% improvement in the figure of merit (FOM). Notably, the proposed structure can be extended to LDMOS devices across different voltage levels within BCD platforms, demonstrating its broad applicability.
1. Introduction
In recent years, rapid developments in the field of automotive electronics and power management integrated circuits (PMIC)[1−3] have generated growing interest in lateral diffused metal−oxide−semiconductor (LDMOS) transistors, owing to their high-voltage tolerance[4], low power consumption[5], and compatibility with conventional CMOS processes[6]. However, the trade-off between specific on-resistance (Ron,sp) and breakdown voltage (BV) remains a major challenge in LDMOS performance optimization[7−9].
Implementing a field plate (FP) in LDMOS is an effective strategy for enhancing BV while reducing Ron,sp[10−13]. This improvement is primarily attributed to three mechanisms: the extension of the depletion region, the introduction of additional electric-field peaks, and the formation of an electron accumulation layer. Owing to its simple fabrication process and significant performance benefits, the FP technique has been widely adopted in low-voltage applications. Recent research has focused on developing novel FP structures to further optimize the BV−Ron,sp trade-off of LDMOS, including: (1) stepped FP[14−16], which modulates the electric-field distribution in the drift region by varying the field-oxide thickness; (2) split FP with positive bias[17, 18], which introduces electric-field peaks and enhances electron accumulation through a positively biased field plate; (3) linear-potential FP[19
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Yiting Ye, Xiaoyun Huang, Yixian Song, Kai Xu (2025). A novel split gate and contact-field-plate LDMOS with enhanced BV−Ron,sp trade-off and improved FOM. SinoTechIntel Verified Research. https://doi.org/10.1088/1674-4926/25080033
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Frequently Asked Questions
What is the main contribution of this paper?
The paper proposes a novel LDMOS structure with a split gate and split contact field plate (CFP) that improves the trade-off between breakdown voltage (BV) and specific on-resistance (Ron,sp) without requiring additional bias voltages, masks, or process steps, making it fully compatible with BCD process flow.
How does the proposed LDMOS achieve lower Ron,sp?
In the on-state, the positively biased split gate forms an accumulation layer at the drift region surface, which reduces the specific on-resistance (Ron,sp).
How does the proposed LDMOS maintain high breakdown voltage?
In the off-state, both the split gate and split CFP introduce additional electric-field peaks that smooth the lateral electric field, thereby preserving a high breakdown voltage (BV).
What are the performance improvements compared to conventional CFP-LDMOS?
Compared to conventional CFP-LDMOS, the proposed structure achieves an 8.52% reduction in Ron,sp without compromising BV, leading to an 8.07% improvement in figure of merit (FOM).
Is the proposed structure compatible with existing manufacturing processes?
Yes, the proposed structure requires no additional bias voltages, masks, or process steps, making it fully compatible with the bipolar-CMOS-DMOS (BCD) process flow.
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