• SAPER-AI achieves 10–25% power efficiency improvement for 32×32 and 64×64 systolic array configurations through coarse-grained row/column PE deactivation.
• The accelerator utilizes Unified Power Format (UPF) for simplified power intent specification, enabling rapid design with negligible microarchitectural optimization effort.
• Power-delay product (PDP) improves by approximately 6% for larger systolic array sizes, demonstrating the scalability of the proposed power management technique.
• ResNet50 workloads consistently outperform MobileNet on systolic arrays due to more regular convolution patterns, with the gap widening as array size increases.