A power optimization approach for mixed polarity Reed–Muller logic circuits based on multi-strategy fusion memetic algorithm

Abstract

The power optimization of mixed polarity Reed–Muller (MPRM) logic circuits is a classic combinatorial optimization problem. Existing optimization approaches often suffer from slow convergence and a propensity to converge to local optima, limiting their effectiveness in achieving optimal power efficiency. First, we propose a novel multi-strategy fusion memetic algorithm (MFMA). MFMA integrates global exploration via the chimp optimization algorithm with local exploration using the coati optimization algorithm based on the optimal position learning and adaptive weight factor (COA-OLA), complemented by population management through truncation selection. Second, leveraging MFMA, we propose a power optimization approach for MPRM logic circuits that searches for the best polarity configuration to minimize circuit power. Experimental results based on Microelectronics Center of North Carolina (MCNC) benchmark circuits demonstrate significant improvements over existing power optimization approaches. MFMA achieves a maximum power saving rate of 72.30% and an average optimization rate of 43.37%; it searches for solutions faster and with higher quality, validating its effectiveness and superiority in power optimization.

1. Introduction

As the integrated circuit (IC) industry rapidly evolves alongside advancements in electronic information technology, the significance of IC in digital systems, computer manufacturing, communication equipment, and various other domains continues to grow (Huan et al., 2021). However, with this rapid progress comes a notable issue: the escalating power of IC. This increase not only poses challenges for portable devices, causing power difficulties and chip overheating, but also impacts the cost of heat dissipation and packaging. Consequently, optimizing chip power has emerged as a pivotal factor in IC design and optimization.

Digital logic circuits can be implemented using either Boolean logic circuits, which rely on AND/OR/NOT operations, or Reed–Muller (RM) logic circuits, which use XNOR/OR or XOR/AND operations. Numerous studies have indicated that for certain circuits (Zhao GC et al., 2024), RM logic circuits offer more significant advantages over Boolean logic circuits in terms of power, area efficiency, reliability, and testability. Consequently, RM logic circuits have garnered considerable attention as research focuses on the field of IC design and optimization (Lopera et al., 2021). The most prevalent forms of RM logic circuits are the XNOR/OR-based mixed polarity RM (MPRM) logic circuits and the XOR/AND-based fixed polarity RM (FPRM) logic circuits. For any n-variable Boolean logic circuit, there exist 3n different mixed polarities and 2n different fixed polarities. As a result, MPRM logic circuits provide a large optimization space and a great potential for improved performance compared to FPRM logic. Furthermore, varying input variables yield different circuit expressions, corresponding to distinct polarities (Liu et al., 2024). Optimizing power in MPRM circuits involves identifying the optimal polarity configuration that minimizes power, thereby posing a typical combinatorial optimization problem.

In MPRM logic circuits, the exhaustive search method effectively finds the optimal polarity for circuits with fewer input variables. However, as the number of input variables increases, the optimization space grows exponentially, making exhaustive methods time-consuming and inefficient, ultimately failing to yield optimal solutions within a reasonable timeframe. Due to their simple structure, fast search capabilities, and resistance to local optima, swarm intelligence optimization algorithms have found widespread application in MPRM circuit optimization.