Key Takeaways & Executive Findings
- •• A silicon-based Schottky barrier MOSFET (SB-MOSFET) fabricated under low thermal budget and compatible with back-end-of-line (BEOL) integration is introduced for neuromorphic computing. • The SB-MOSFET exhibits short-term memory characteristics via modulation of Schottky barriers and charge trapping, enabling reservoir computing for temporal data processing. • The reservoir computing system achieves over 98% accuracy in a 5×4 digital classification task after 50 training epochs, and successfully handles waveform classification and prediction tasks. • The high CMOS compatibility of the SB-MOSFET offers significant advantages for large-scale integration, paving the way for energy-efficient reservoir computing hardware.
Abstract
Neuromorphic devices have garnered significant attention as potential building blocks for energy-efficient hardware systems owing to their capacity to emulate the computational efficiency of the brain. In this regard, reservoir computing (RC) framework, which leverages straightforward training methods and efficient temporal signal processing, has emerged as a promising scheme. While various physical reservoir devices, including ferroelectric, optoelectronic, and memristor-based systems, have been demonstrated, many still face challenges related to compatibility with mainstream complementary metal oxide semiconductor (CMOS) integration processes. This study introduced a silicon-based schottky barrier metal−oxide−semiconductor field effect transistor (SB-MOSFET), which was fabricated under low thermal budget and compatible with back-end-of-line (BEOL). The device demonstrated short-term memory characteristics, facilitated by the modulation of schottky barriers and charge trapping. Utilizing these characteristics, a RC system for temporal data processing was constructed, and its performance was validated in a 5 × 4 digital classification task, achieving an accuracy exceeding 98% after 50 training epochs. Furthermore, the system successfully processed temporal signal in waveform classification and prediction tasks using time-division multiplexing. Overall, the SB-MOSFET's high compatibility with CMOS technology provides substantial advantages for large-scale integration, enabling the development of energy-efficient reservoir computing hardware.
1. Introduction
The rapid advance of machine learning algorithms has catalyzed a new generation of artificial intelligence (AI) applications, ranging from biomedicine to autonomous driving. These breakthroughs are underpinned by artificial neural networks (ANNs), which emulate biological neural activity through weighted, structured interactions among interconnected nodes. ANNs are typically classified by their feedback topology: feedforward architectures—exemplified by convolutional neural networks (CNNs)—excel at static image analysis, whereas recurrent neural networks (RNNs) are preferred for temporal-sequence processing. Nevertheless, training RNNs is often challenging due to issues such as vanishing or exploding gradients, which hinder their practical deployment.
Reservoir computing (RC) has emerged as a promising alternative to traditional RNNs, offering a simplified training paradigm by keeping the recurrent connections fixed and only training the readout layer. This approach significantly reduces computational cost and has been successfully applied to various temporal tasks. Physical implementations of RC have been demonstrated using a variety of devices, including ferroelectric, optoelectronic, and memristor-based systems. However, many of these devices face compatibility issues with mainstream CMOS fabrication processes, limiting their scalability and integration with existing electronics.
In this work, we propose a silicon-based Schottky barrier MOSFET (SB-MOSFET) fabricated under a low thermal budget, making it compatible with back-end-of-line (BEOL) integration. The device leverages Schottky barrier modulation and charge trapping to exhibit short-term memory characteristics, which are essential for reservoir computing. We demonstrate the effectiveness of this device in a reservoir computing system for temporal data classification, achieving high accuracy in digital classification and waveform prediction tasks. The CMOS-compatible fabrication process and promising performance highlight the potential of SB-MOSFETs for large-scale, energy-efficient neuromorphic hardware.
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Yanqing Li, Feixiong Wang, Heyi Huang, Yadong Zhang, Xiangpeng Liang, Shuang Liu, Jianshi Tang, Huaxiang Yin (2025). A low-thermal-budget MOSFET-based reservoir computing for temporal data classification. SinoTechIntel Verified Research. https://doi.org/10.1088/1674-4926/25080038
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Frequently Asked Questions
What is the main contribution of this paper?
The paper introduces a silicon-based Schottky barrier MOSFET (SB-MOSFET) fabricated under low thermal budget and compatible with back-end-of-line (BEOL) integration. It demonstrates short-term memory characteristics and successfully implements a reservoir computing system for temporal data classification, achieving over 98% accuracy in a digital classification task.
How does the SB-MOSFET achieve short-term memory?
The SB-MOSFET achieves short-term memory through the modulation of Schottky barriers and charge trapping. These mechanisms allow the device to retain information temporarily, which is essential for processing temporal sequences in reservoir computing.
What are the advantages of using SB-MOSFET for reservoir computing?
The SB-MOSFET offers high compatibility with CMOS fabrication processes, enabling large-scale integration. Additionally, its low thermal budget fabrication makes it suitable for back-end-of-line integration, which is advantageous for building energy-efficient neuromorphic hardware.
What tasks were used to validate the reservoir computing system?
The reservoir computing system was validated on a 5×4 digital classification task, achieving over 98% accuracy after 50 training epochs. It also successfully processed temporal signals in waveform classification and prediction tasks using time-division multiplexing.
What is the significance of this work for future neuromorphic computing?
This work demonstrates a CMOS-compatible device that can be used for reservoir computing, addressing the scalability and integration challenges faced by many physical reservoir devices. It paves the way for developing large-scale, energy-efficient neuromorphic hardware that can be integrated with existing semiconductor technology.
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