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A high reliability NOR flash cell in 50 nm node technology

Authors: Kevin Fang; Wei Wang; Yibai Xue; Fan Wang; Dong Pan; Yi Li; Jerry Zhou

DOI: 10.1088/1674-4926/25030030Status: Verified Translated Edition
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Key Findings in This Report

• Structural optimization of floating gate dimensions and active area profile expands control gate-to-active area corner distance by 22%, suppressing peak electric fields by 29% vertically and 18% horizontally. • The optimized NOR flash cell achieves 100× reduction in early-cycle burnout failures and 7.38× improvement in time dependent dielectric breakdown lifetime. • Programming and erasing speeds are accelerated by 15.4% and 7.3%, respectively, while data retention is maintained. • The enhanced reliability enables a 97.5% reduction in Fowler-Nordheim stress time during characterization program testing, offering a cost-effective solution for automotive-grade flash memories.