Key Takeaways & Executive Findings
- •• A 32 Gb/s PAM-4 DFB laser driver in 28-nm CMOS achieves high linearity via a digital slicing architecture with three thermometer-coded main paths. • An efficient-biased output stage reduces power consumption without sacrificing output node bandwidth, addressing parasitic capacitance issues. • A two-tap linear and nonlinear FFE in the digital domain extends bandwidth and compensates for DFB laser dynamic nonlinearity, with low power and area overhead. • Measured at 32 Gb/s PAM-4 with 40 mA bias and 20 mApp modulation, the driver consumes 372 mW, achieving an energy efficiency of 11.6 pJ/b.
Abstract
This paper presents a 4-level pulse amplitude modulation (PAM-4) distributed feedback (DFB) laser driver. The driver adopts a digital slicing architecture to achieve high linearity by adjusting the weights of three thermometer-coded main paths. An efficient-biased output stage structure is proposed to reduce power consumption while avoiding the degradation of output node bandwidth typically induced by parasitic capacitance in high-current bias path. A two-tap linear and nonlinear feed-forward equalizer (FFE) is implemented in the digital domain to extend bandwidth limitations and compensate for the dynamic nonlinearity of the DFB laser. The nonlinear FFE is realized at the cost of lower power consumption and smaller area by utilizing the simultaneity of low-speed parallel data. The chip is fabricated in 28 nm CMOS process. Measurement results indicate that, with a laser bias current of 40 mA, a modulation current of 20 mApp, and an operating rate of 32 Gb/s PAM-4, the overall power consumption of the chip is 372 mW, corresponding to an energy efficiency of 11.6 pJ/b.
1. Introduction
With the rapid development of the datacenter and artificial intelligence, data volumes have grown exponentially, increasing the demand for high-bandwidth and low-power data transmission. Traditional electrical links suffer from significant channel loss at distances greater than ten meters, which becomes more pronounced as the symbol rates surpass 25 GBaud. In contrast, optical interconnection utilizes optical fiber as the transmission medium, offering extremely wideband and the ability to transmit data over long distances. Consequently, optical interconnection has become a focal point of research in the field of wired communication[1−4].
Optical transmitters typically comprise an electrical driver chip and an optical device. The electrical chip drives the optical device to transform the electrical signal into an optical signal. Optical devices are generally categorized into directly modulated lasers (DML) and externally modulated lasers (EML). A directly mo
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Yang Min, Nan Qi, Yihan Chen, Minye Zhu, Guike Li, Yonghui Lin, Zhao Zhang, Jian Liu, Nanjian Wu, Jingbo Shi, Frank F. Shi, Liyuan Liu (2025). A 32Gb/s digital-assisted PAM-4 DFB laser driver in 28-nm CMOS. SinoTechIntel Verified Research. https://doi.org/10.1088/1674-4926/25020011
Research & Educational Purpose Only:The translations, structured abstracts, analytical annotations, and data reports provided by SinoTechIntel are intended exclusively for academic research, internal corporate R&D, and educational benchmarking. They do not constitute formal engineering, chemical safety, legal, or professional advice.
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Frequently Asked Questions
What is the operating rate and modulation scheme of the proposed laser driver?
The proposed laser driver operates at 32 Gb/s using 4-level pulse amplitude modulation (PAM-4).
How does the driver achieve high linearity?
The driver uses a digital slicing architecture with three thermometer-coded main paths, whose weights are adjusted to achieve high linearity.
What is the power consumption and energy efficiency of the chip?
At 32 Gb/s PAM-4 with 40 mA bias and 20 mApp modulation, the chip consumes 372 mW, corresponding to an energy efficiency of 11.6 pJ/b.
What is the purpose of the nonlinear FFE in the driver?
The two-tap linear and nonlinear FFE extends bandwidth limitations and compensates for the dynamic nonlinearity of the DFB laser, while achieving low power and small area.
In which CMOS process is the chip fabricated?
The chip is fabricated in a 28-nm CMOS process.
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